IP Library Granted Patent US 12,159,876
Granted Patent B2
US 12,159,876 · App. 18/459,677 · Granted Dec 3, 2024

Display device

Inventor: Isao Suzumura (Tokyo, JP)
Assignee: Japan Display Inc.
H01L27/1225G02F1/1368H01L27/1248H01L29/401H01L29/42384H10K59/126G02F1/13685H01L21/426
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Quick Facts
Patent No.
US 12,159,876
App. No.
18/459,677
Granted
Dec 3, 2024
Kind
B2
Abstract

The purpose of the present invention is to decrease the resistance of the drain and source in the TFT of the oxide semiconductor as well as to have stable Vd-Id characteristics of the TFT. The structure of the present invention is as follows: A display device having plural pixels including thin film transistors (TFT) having oxide semiconductor films comprising: a gate insulating film formed on the oxide semiconductor film, an aluminum oxide film formed on the gate insulating film, a gate electrode formed on the aluminum oxide film, a side spacer formed on both sides of the gate electrode, and an interlayer insulating film formed on the gate electrode, the side spacer, a drain and a source, wherein in a plan view, and in a direction from the drain to the source, a length of the gate electrode is shorter than a length of the aluminum oxide film.

Claims (12)

1. A semiconductor device having thin film transistors comprising: oxide semiconductor film, drain, source, a gate insulating film formed on the oxide semiconductor film, an aluminum oxide film formed on the gate insulating film, a gate electrode and a side spacer formed on the aluminum oxide film, and an interlayer insulating film formed on the gate electrode, the side spacer, the drain and the source, wherein in a plan view, and in a direction from the drain to the source, a length of the gate electrode is shorter than a length of the aluminum oxide film, the gate electrode covers an inner surface of the side spacer and a top surface of the side spacer, a side surface, which contacts with the interlayer insulating film, of the side spacer is a tapered surface.

2. The semiconductor device according to claim 1 ,

wherein a length, in the direction from the drain to the source, of the gate electrode on the top of the side spacer is 0.1 microns or more.

3. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor film has a channel, which is formed between the drain and the source,

an intermediate region is formed between the channel and the drain and between the channel and the source,

a gate insulating film is formed on the channel and the intermediate region of the oxide semiconductor film,

the gate electrode is formed on the aluminum oxide film above the channel, and

a content of hydrogen in the oxide semiconductor film, is: in the channel<in the intermediate region<in the drain or the source.

4. The semiconductor device according to claim 1 ,

wherein a content of hydrogen in the interlayer insulating film is higher than a content of hydrogen in the side spacer.

5. The semiconductor device according to claim 1 , wherein a height of the side spacer is 100 to 500 nm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
Priority Claims (1)
JP 2018-002641 · Jan 11, 2018 · national
Continuity (4)
Continuation 17694754 · Mar 15, 2022
Continuation 16922438 · Jul 7, 2020
Continuation PCTJP2018043661 · Nov 28, 2018
Related Publication 20230411401A1 · Dec 21, 2023
Cited By (1)
US 12,563,716