IP Library › Granted Patent US 12,176,267
Granted Patent B2
US 12,176,267 · App. 18/382,203 · Granted Dec 24, 2024

Semiconductor device and method for manufacturing the same

Inventor: Liang-Pin Chou (Taoyuan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L23/481H01L21/76838H01L21/76898H01L23/5226H01L23/53238
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Quick Facts
Patent No.
US 12,176,267
App. No.
18/382,203
Granted
Dec 24, 2024
Kind
B2
Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Claims (37)

1. A semiconductor device, comprising:

a first die structure;

a second die structure, wherein the first die structure is stacked over the second die structure;

an intervening bonding layer positioned on the first die structure opposite to the second die structure;

a carrier structure disposed on the intervening bonding layer opposite to the first die structure; and

a first dummy through semiconductor via, configured to transfer heat accumulated in the first die structure and the second die structure, comprising:

a first via;

a second via extended spaced apart from the first via; and

a first bottom conductive connecting portion, electrically coupled to bottom portions of the first via and the second via, wherein top portions of the first via and the second via are protruded from the first bottom conductive connecting portion.

2. The semiconductor device of claim 1 , further comprising a first protection layer surrounding the first via and a second protection layer surrounding the second via, wherein a width of the first via is greater than a width of the second via, wherein the bottom portions of the first via and the second via are exposed from the first protection layer and the second protection layer respectively.

3. The semiconductor device of claim 1 , wherein a length of the first via is equal to a length of the second via, wherein the first via and the second via are parallel with each other.

4. The semiconductor device of claim 1 , wherein the carrier structure comprises:

a bonding layer, disposed over the intervening bonding layer;

a carrier substrate, disposed over the bonding layer; and

a heat dissipation unit, disposed in the bonding layer and the carrier substrate.

5. The semiconductor device of claim 4 , wherein the heat dissipation unit comprises:

a plurality of first composite vias;

a plurality of second composite vias;

a first conductive plate, coupled to the plurality of first composite vias; and

a second conductive plate, coupled to the plurality of second composite vias.

6. The semiconductor device of claim 1 , wherein the first via and the second via are extending through the first die structure and the second die structure.

7. The semiconductor device of claim 6 , wherein the top portions of the first via and the second via are in contact with the intervening bonding layer.

8. The semiconductor device of claim 6 , wherein the top portions of the first via and the second via are in contact with the carrier structure.

9. The semiconductor device of claim 1 , further comprising:

a second dummy through semiconductor via, configured to transfer heat accumulated in the first die structure and the second die structure, comprising:

a third via;

a fourth via extended spaced apart from the third via; and

a second bottom conductive connecting portion, electrically coupled to bottom portions of the third via and the fourth via, wherein top portions of the third via and the fourth via are protruded from the second bottom conductive connecting portion.

10. The semiconductor device of claim 9 , wherein a length of the first dummy through semiconductor via is greater than a length of the second dummy through semiconductor via.

11. The semiconductor device of claim 9 , wherein the second dummy through semiconductor via is disposed in the first die structure and the second die structure, and is not exposed by the second die structure.

12. The semiconductor device of claim 9 , further comprising:

a third dummy through semiconductor via, configured to transfer heat accumulated in the first die structure and the second die structure, comprising:

a fifth via;

a sixth via extended spaced apart from the fifth via; and

a third bottom conductive connecting portion, electrically coupled to bottom portions of the fifth via and the sixth via, wherein top portions of the fifth via and the sixth via are protruded from the third bottom conductive connecting portion.

13. The semiconductor device of claim 12 , wherein a length of the second dummy through semiconductor via is greater than a length of the third dummy through semiconductor via.

14. The semiconductor device of claim 12 , wherein the third dummy through semiconductor via is disposed in the first die structure, and is not in contact with the second die structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2023
From: CHOU, LIANG-PIN
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 065295/0078 →
Continuity (4)
Division 18208510 · Jun 12, 2023
Continuation In Part 17411678 · Aug 25, 2021
Division 16440112 · Jun 13, 2019
Related Publication 20240047307A1 · Feb 8, 2024