Method of manufacturing semiconductor devices and semiconductor devices
In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.
1. A semiconductor device, comprising:
a first field effect transistor (FET) including a first gate structure disposed over a first channel region;
a second FET including a second gate structure disposed over a second channel region; and
a third FET including a third gate structure disposed over a third channel region, wherein:
a threshold voltage of the first FET is different from a threshold voltage of the second FET and a threshold voltage of the third FET,
each of the first, second, and third gate structures includes:
a gate dielectric layer;
a first work function adjustment layer over the gate dielectric layer;
a metal gate electrode layer disposed over the first work function adjustment layer; and
a first metal nitride layer disposed between the gate dielectric layer and the first work function adjustment layer,
wherein the second and third gate structures further include:
a second work function adjustment layer made of a different material than the first work function adjustment layer disposed between the first work function adjustment layer and the first metal nitride layer; and
a second metal nitride layer disposed between the second work function adjustment layer and the first metal nitride layer,
wherein the first gate structure does not include the second metal nitride layer,
a thickness of the first metal nitride layer in the first gate structure is smaller than a thickness of the first metal nitride layer in the second gate structure and the third gate structure, and
a thickness of the second metal nitride layer in the second gate structure and the third gate structure is less than a thickness of the first metal nitride layer in the second gate structure and the third gate structure.
2. The semiconductor device of claim 1 , wherein the first metal nitride layer is made of TiN or TiN doped with Si and the second metal nitride layer is made of TaN.
3. The semiconductor device of claim 1 , wherein the first gate structure includes no second work function adjustment layer.
4. The semiconductor device of claim 1 , wherein:
the first work function adjustment layer includes aluminum, and
the second work function adjustment layer includes TiN.
5. The semiconductor device of claim 1 , wherein the metal gate electrode layer includes a glue layer and a body metal layer.
6. The semiconductor device of claim 1 , wherein the first FET is a fin FET including a fin structure, a part of which is the first channel region, and the second FET is a fin FET including a fin structure, a part of which is the second channel region.
7. A semiconductor device, comprising:
a first field effect transistor (FET) including a first gate structure disposed over a first channel region;
a second FET including a second gate structure disposed over a second channel region; and
a third FET including a third gate structure disposed over a third channel region, wherein:
a threshold voltage of the first FET is smaller, in an absolute value, than a threshold voltage of the second FET, and the threshold voltage of the second FET is smaller, in an absolute value, than a threshold voltage of the third FET,
each of the first, second and third gate structures includes:
a gate dielectric layer;
a first work function adjustment layer over the gate dielectric layer;
a metal gate electrode layer disposed over the first work function adjustment layer,
wherein the second and third gate structures further include a first barrier layer below the first work function adjustment layer, and the first gate structure includes no first barrier layer,
the first, second and third gate structures further include a second barrier layer on the gate dielectric layer, and
a thickness of the second barrier layer in the first gate structure is smaller than a thickness of the second barrier layer in the second gate structure and the third gate structure.
8. The semiconductor device of claim 7 , wherein the second barrier layer is made of TiN or TiN doped with Si and the first barrier layer is made of TaN.
9. The semiconductor device of claim 7 , wherein the second and third gate structure further include a second work function adjustment layer made of a different material than the first work function adjustment layer, and the first gate structure includes no second work function adjustment layer.
10. The semiconductor device of claim 9 , wherein a thickness of the second work function adjustment layer in the second gate structure is smaller than a thickness of the second work function adjustment layer in the third gate structure.
11. The semiconductor device of claim 9 , wherein:
the first work function adjustment layer is made of one selected from the group consisting of TiAl, TiAlC, TaAl, TaAlC and TiAlN.
12. The semiconductor device of claim 11 , wherein the second work function adjustment layer includes TiN.
13. The semiconductor device of claim 7 , wherein the metal gate electrode layer includes a glue layer and a body metal layer.
14. The semiconductor device of claim 13 , wherein the glue layer includes TiN and the body metal layer includes W.
15. A semiconductor device, comprising:
a first field effect transistor (FET) including a first gate structure disposed over a first channel region;
a second FET including a second gate structure disposed over a second channel region; and
a third FET including a third gate structure disposed over a third channel region, wherein:
a threshold voltage of the first FET is smaller, in an absolute value, than a threshold voltage of the second FET, and the threshold voltage of the second FET is smaller, in an absolute value, than a threshold voltage of the third FET,
each of the first, second and third gate structures includes:
a gate dielectric layer;
a first work function adjustment layer over the gate dielectric layer;
a metal gate electrode layer disposed over the first work function adjustment layer; and
a first barrier layer on the gate dielectric layer,
wherein the second and third gate structures further include a second work function adjustment layer made of a different material than the first work function adjustment layer disposed between the first work function adjustment layer and the first barrier layer,
the second and third gate structures include a second barrier layer disposed between the first barrier layer and the second work function adjustment layer, and
a thickness of the first barrier layer in the first gate structure is smaller than a thickness of the first barrier layer in the second gate structure and the third gate structure.
16. The semiconductor device of claim 15 , wherein the first gate structure includes no second work function adjustment layer.
17. The semiconductor device of claim 15 , wherein in the first gate structure, the first work function adjustment layer is in direct contact with the first barrier layer.
18. The semiconductor device of claim 15 , wherein a thickness of the second work function adjustment layer in the second gate structure is smaller than a thickness of the second work function adjustment layer in the third gate structure.
19. The semiconductor device of claim 15 , wherein the first work function adjustment layer is made of one selected from the group consisting of TiAl, TiAlC, TaAl, TaAlC and TiAlN.
20. The semiconductor device of claim 19 , wherein the second work function adjustment layer includes one of MoN, WCN or WN.