Polishing pad, method for manufacturing polishing pad, and polishing method
Disclosed is a polishing pad including a polishing layer having a polishing surface, wherein the polishing surface includes a deep-groove region having a first pattern formed by a deep groove or hole having a depth of 0.3 mm or more, and a land region that is a region other than the deep-groove region, and the land region includes shallow recesses having a second pattern and a depth of 0.01 to 0.1 mm, and a plurality of island-like land portions surrounded by the shallow recesses and having a maximum distance in a horizontal direction of 8 mm or less.
1. A polishing pad, comprising:
a polishing layer having a polishing surface,
wherein the polishing surface includes a deep-groove region having a first pattern formed by a deep groove or hole having a depth of 0.3 mm or more, and a land region that is a region other than the deep-groove region,
the land region includes shallow recesses having a second pattern, a depth of 0.01 to 0.1 mm and a width of 0.5 to 4 mm, and a plurality of island-like land portions surrounded by the shallow recesses and having a maximum distance in a horizontal direction of 0.5 to 8 mm, and
wherein each of said depths is based on the depth on a polishing surface of an unused polishing pad which has not undergone a break-in treatment.
2. The polishing pad according to claim 1 ,
wherein the second pattern includes at least one pattern formed on the entire surface of the land region selected from the group consisting of a triangular grid pattern, a square grid pattern, a rectangular grid pattern, a diamond-shaped grid pattern, and a hexagonal grid pattern.
3. The polishing pad according to claim 2 ,
wherein the first pattern has a groove pitch of 1 to 15 mm and a groove width of 0.1 to 4 mm.
4. The polishing pad according to claim 2 ,
wherein the shallow recesses have a width of 1 to 2 mm and the first pattern has a groove pitch of 1 to 15 mm and a groove width of 0.1 to 4 mm.
5. The polishing pad according to claim 2 ,
wherein a projected area of each one of the land portions is in the range of 1.5 to 5 mm 2 .
6. The polishing pad according to claim 1 ,
wherein a projected area of each one of the land portions is in the range of 0.3 to 10 mm 2 .
7. The polishing pad according to claim 1 ,
wherein a ratio of a total projected area of the land portions to an overall projected area of the land region is 10 to 50%.
8. The polishing pad according to claim 1 ,
wherein the depth of the shallow recesses is 0.02 to 0.06 mm.
9. The polishing pad according to claim 1 ,
wherein a ratio of a projected area of the deep-groove region to an overall projected area of the polishing surface is 5 to 40%.
10. The polishing pad according to claim 1 ,
wherein the first pattern includes at least one pattern selected from the group consisting of a spiral pattern, a concentric pattern, and a grid pattern.
11. The polishing pad according to claim 1 ,
wherein the polishing layer is formed of a sheet composed mainly of a non-foamed polymer body.
12. The polishing pad according to claim 1 ,
wherein the polishing layer includes a thermoplastic polyurethane sheet.
13. A method for manufacturing the polishing pad according to claim 1 , the method comprising:
preparing a polymer sheet for forming the polishing layer;
forming the deep-groove region on a side of the polymer sheet serving as a polishing surface; and
forming the land region on the side the polymer sheet serving as the polishing surface, wherein the shallow recesses are formed by cutting or transferring.
14. A polishing method for polishing a surface of a semiconductor device in a manufacturing process of the semiconductor device, the method comprising:
conditioning the polishing surface of the polishing pad according to claim 1 during a break-in of the polishing pad under conditions where, for an accumulated conditioning time of 30 minutes or less, an average depth of the shallow recesses with the depth of 0.01 to 0.1 mm becomes less than 0.01 mm to produce a broken-in polishing pad; and
polishing the surface of the semiconductor device using the broken-in polishing pad.
15. The polishing method according to claim 14 ,
wherein the accumulated conditioning time is 1 to 20 minutes.
16. The polishing pad according to claim 1 ,
wherein the shallow recesses have a width of 1 to 2 mm.
17. The polishing pad according to claim 1 ,
wherein the first pattern has a groove pitch of 1 to 15 mm and a groove width of 0.1 to 4 mm.
18. The polishing pad according to claim 1 ,
wherein the shallow recesses have a width of 1 to 2 mm and the first pattern has a groove pitch of 1 to 15 mm and a groove width of 0.1 to 4 mm.
19. The polishing pad according to claim 1 ,
wherein a projected area of each one of the land portions is in the range of 1.5 to 5 mm 2 .
20. The polishing pad according to claim 1 , wherein:
the first pattern includes at least one pattern selected from the group consisting of a spiral pattern, a concentric pattern, and a grid pattern, and
the second pattern includes at least one pattern formed on the entire surface of the land region selected from the group consisting of a triangular grid pattern, a square grid pattern, a rectangular grid pattern, a diamond-shaped grid pattern, and a hexagonal grid pattern.