Customized smart devices and touchscreen devices and cleanspace manufacturing methods to make them
View Patent ↗The present invention provides various aspects for processing multiple types of substrates within cleanspace fabricators or for processing multiple or single types of substrates in multiple types of cleanspace environments particularly to form hardware based encryption devices and hardware based encryption equipped communication devices and multi-chip modules such as chiplets. In some embodiments, a collocated composite cleanspace fabricator may be capable of processing semiconductor devices into integrated circuits and then performing assembly operations to result in product in packaged form. Customized smart devices, smart phones and touchscreen devices may be fabricated in examples of a cleanspace fabricator. The assembly processing may include steps to form hardware based encryption.
1. A method of forming a 3DIC multi-chip module, the method comprising:
configuring a cleanspace fabricator, wherein the cleanspace fabricator is configured to process at least a first substrate comprising integrated circuits of a first design and a second substrate comprising integrated circuits of a second design, wherein the cleanspace fabricator maintains a particulate cleanliness in a primary cleanspace of the cleanspace fabricator, wherein the cleanspace fabricator comprises at least a first processing apparatus in a first toolpod and a second processing apparatus in a second toolpod deployed in operating positions along a periphery of the cleanspace fabricator, wherein a bottom of the first toolpod is located vertically above a top of the second toolpod when in their respective operating positions, and wherein the cleanspace fabricator comprises fabricator automation to move at least one or more of the first substrate and the first processing apparatus within the primary cleanspace of the cleanspace fabricator;
positioning a third toolpod into a third position along the periphery of the cleanspace fabricator;
moving the third toolpod into an operating position of the third position, wherein a tool port of the third toolpod in the operating position of the third position interfaces with the primary cleanspace;
processing the first substrate in the first processing apparatus in the first toolpod, wherein the processing of the first substrate in the first processing apparatus performs at least a first processing step in the processing of the integrated circuits of a first design;
moving the first substrate to the second processing apparatus in the second toolpod, wherein the first substrate is moved through the primary cleanspace;
processing the first substrate in the second processing apparatus in the second toolpod, wherein the processing of the first substrate in the second processing apparatus performs at least a first processing step in creating a thru silicon via in the first substrate;
moving the first substrate to the third processing apparatus in the third toolpod, wherein the first substrate is moved through the primary cleanspace;
processing the first substrate in the third processing apparatus to isolate a first integrated circuit of the first design from the first substrate;
moving the first integrated circuit of the first design to a fourth processing apparatus in a fourth toolpod, wherein the fourth toolpod is positioned into an operating position of the cleanspace fabricator;
moving the second substrate to the second processing apparatus in the second toolpod, wherein the second substrate is moved through the primary cleanspace;
processing the second substrate in the second processing apparatus in the second toolpod, wherein the processing of the second substrate in the second processing apparatus performs at least a first processing step in creating a thru silicon via in the second substrate;
moving the second substrate to the third processing apparatus in the third toolpod, wherein the second substrate is moved through the primary cleanspace;
processing the second substrate in the third processing apparatus to isolate a second integrated circuit of the second design from the second substrate;
moving the second integrated circuit of the first design to the fourth processing apparatus in the fourth toolpod; and
processing the first integrated circuit in the fourth processing apparatus in the fourth toolpod to affix the first integrated circuit to a third substrate; and
processing the second integrated circuit in the fourth processing apparatus in the fourth toolpod to affix the second integrated circuit to the third substrate to form the 3DIC multi-chip module.
2. The method of claim 1 wherein the integrated circuits of a first design are formed on a substrate of a thickness of about 280 microns and the integrated circuits of the second design are formed on a substrate with a thin center and an edge ring of a thickness of about 280 microns.
3. The method of claim 1 wherein the integrated circuits of a first design are formed in silicon and the integrated circuits of the second design are formed in non-silicon.
4. The method of claim 1 wherein the third substrate comprises an interposer.
5. The method of claim 4 wherein the third substrate further comprises a first touch screen.
6. The method of claim 5 further comprising adding a second touch screen to a second side of the third substrate, wherein the second side is on a distal location to a first side of the third substrate where the first touch screen is located.
7. The method of claim 1 wherein the first integrated circuit is a unique hardware based encryption chip wherein the unique hardware based encryption chip is formed by a method comprising:
assembling the unique hardware based encryption chip into a package and depositing a first encapsulating layer upon the unique hardware based encryption chip; and
depositing a first conductive film, wherein the first conductive film is a portion of a stack of encapsulating films which encapsulate at least the hardware encryption integrated circuit.
8. The method of claim 7 wherein formation of the unique hardware based encryption chip further comprises:
imaging a pattern of interconnect pathways and connection pads into the first conductive film using photolithography and a photoresist system;
etching the pattern of interconnect pathways and connection pads into the first conductive film based on the imaged pattern;
removing residual photoresist;
placing a film upon the connection pads, wherein the film has a characteristic that can be measured electrically at the connection pads, and wherein the characteristic may be modulated by selective processing of the film;
modulating a physical characteristic of the film with a laser irradiation process; and
depositing a second conductive film upon the film, wherein a connection pad outside the second conductive film electrically connects the second conductive film to a second electrical connection pad of the hardware encryption integrated circuit.
9. The method of claim 8 wherein the first conductive film comprises graphene.
10. The method of claim 9 further comprising a reactive multilevel foil, wherein the reactive multilevel foil is activated with one or more of an electrical current activation, a thermal activation or a mechanical activation process, and where an activation of the reactive multilevel foil releases thermal energy in a brief and significant manner to destruct any information within the film placed upon conduction pads.
11. The method of claim 10 wherein the reactive multilevel foil is a nano reactive multi-layer foil.
12. The method of claim 5 wherein the first touch screen is functional as an output screen of a smart device.
13. The method of claim 1 wherein the second substrate is passed into the cleanspace fabricator through an input/output toolpod.
14. The method of claim 13 wherein a processing step of the second substrate is completed before the second substrate is passed into the cleanspace fabricator.
15. The method of claim 1 further comprising a step of assembling a hazardous material onto one or more of the third substrate.
16. The method of claim 15 wherein the hazardous material of claim 15 is an explosive.
17. The method of claim 1 further comprising adding an encapsulation layer with an additive manufacturing process to the 3DIC multi-chip module.
18. The method of claim 1 wherein the 3DIC multi-chip module is designed for use in a smart device.
19. The method of claim 1 wherein the 3DIC multi-chip module is used for an encryption board for a server.
20. The method of claim 1 wherein the 3DIC multi-chip module is packaged in a fifth toolpod and passed outside the cleanspace fabricator through a sixth toolpod.