Power semiconductor apparatus and fabrication method for the same
The power semiconductor apparatus includes: a semiconductor device 401 ; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420 b having a CTE equal to or less than 5×10 −6 /° C., for example; and a first metal layer 420 a and a third metal layer 420 c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
1. A semiconductor device comprising:
an insulating substrate including a substrate surface and a substrate back surface;
a plurality of wiring patterns formed on the substrate surface;
a semiconductor power device disposed on a first wiring pattern of the plurality of wiring patterns and comprising a first pad electrode and a second pad electrode on a surface thereof;
at least one of a metallic plate and a metal layer disposed on the first pad electrode; and
a metal lead having a first end disposed on an upper surface of the at least one of the metallic plate and the metal layer and the other end connected to a second wiring pattern of the plurality of wiring patterns, wherein
a first melted portion is formed between the metal lead and the at least one of the metallic plate and the metal layer so as to reach an intermediate depth of the at least one of the metallic plate and the metal layer.
2. The semiconductor device according to claim 1 , wherein
the first melted portion including the metal lead and/or the at least one of the metallic plate and the metal layer has been resolidified.
3. The semiconductor device according to claim 1 , further comprising
a first bonding wire connected to the first pad electrode, wherein
the at least one of the metallic plate and the metal layer is not disposed above a portion to which the first bonding wire is connected.
4. The semiconductor device according to claim 1 , further comprising
a second bonding wire connected to the second pad electrode, wherein
the metallic plate is not disposed above a portion to which the second bonding wire is connected.
5. The semiconductor device according to claim 1 , further comprising
a second bonding layer disposed between the first pad electrode and the metallic plate.
6. The semiconductor device according to claim 5 , wherein
the second bonding layer comprises an Ag fired layer or a Cu fired layer.
7. The semiconductor device according to claim 1 , further comprising
a gate metal lead connected to the second pad electrode.
8. The semiconductor device according to claim 1 , wherein
the metallic plate or the metal layer is also disposed on the second pad electrode.
9. The semiconductor device according to claim 1 , wherein
a plurality of the semiconductor power devices are disposed on the substrate to be connected to one another in parallel.
10. The semiconductor device according to claim 1 , wherein
the semiconductor power device is a SiC based MOSFET, the first pad electrode is a source pad electrode, the second pad electrode is a gate pad electrode, and a drain electrode is formed on a back surface of the semiconductor power device.
11. The semiconductor device according to claim 1 , wherein
the metal lead includes one selected from the group consisting of copper, a copper alloy, aluminum, an aluminum alloy, a Fe—Ni based alloy, and a Fe—Ni—Co based alloy.
12. The semiconductor device according to claim 1 , further comprising
a third bonding layer disposed on the substrate surface, wherein
the semiconductor power device is disposed via the third bonding layer on the substrate surface.
13. The semiconductor device according to claim 1 , wherein
the substrate is one selected from the group consisting of a DBC substrate, a DBA substrate, and an AMB substrate.
14. The semiconductor device according to claim 1 , wherein
the substrate is an organic insulating resin layer.
15. The semiconductor device according to claim 1 , further comprising
a second melted portion disposed between the metal lead and the second wiring patterns.
16. The semiconductor device according to claim 15 , wherein
a length of the second melted portion in a depth direction is shorter than a sum of a thickness of the metal lead and a thickness of the second wiring pattern.
17. The semiconductor device according to claim 15 , wherein
a plurality of the second melted portions are formed.
18. The semiconductor device according to claim 1 , wherein
the metallic plate includes one selected from the group consisting of copper, a copper alloy, aluminum, an aluminum alloy, stainless steel, ferrum, and an iron alloy.
19. The semiconductor device according to claim 1 , wherein
one selected from the group consisting of a 1-in-1 module, a 2-in-1 module, a 4-in-1 module, a 6-in-1 module, a 7-in-1 module, an 8-in-1 module, a 12-in-1 module, and a 14-in-1 module is composed by using the semiconductor power devices.
20. The semiconductor device according to claim 1 , wherein
an inverter circuit device or a converter circuit is configured by connecting the semiconductor power devices in series between a first power source and a second power source, by using a plurality of switching circuits using a connecting point between the semiconductor power devices connected in series as an output, and by individually controlling each gate of the semiconductor power devices.
21. The semiconductor device according to claim 1 , wherein
a length of the first melted portion in a depth direction is shorter than a sum of a thickness of the metal lead and a thickness of the at least one of the metal plate and the metal layer.
22. The semiconductor device according to claim 1 , wherein
the first melted portion is formed so as to pass through the metal lead and extend in a vertical direction toward the semiconductor power device.
23. The semiconductor device according to claim 1 , wherein
a plurality of the first melted portions are formed.
24. A semiconductor device comprising:
an insulating substrate including a substrate surface and a substrate back surface;
a plurality of wiring patterns formed on the substrate surface;
a semiconductor power device disposed on a first wiring pattern of the plurality of wiring patterns and comprising a first pad electrode and a second pad electrode on a surface thereof;
a first bonding layer disposed on the first pad electrode; and
a metal lead having a first end disposed on an upper surface of the first bonding layer and the other end connected to a second wiring pattern of the plurality of wiring patterns, wherein
a first melted portion is formed between the metal lead and the first bonding layer so as to reach an intermediate depth of the first bonding layer.
25. The semiconductor device according to claim 24 , wherein
the first melted portion including the metal lead and/or the first bonding layer has been resolidified.
26. The semiconductor device according to claim 24 , further comprising
a first bonding wire connected to the first pad electrode, wherein
the first bonding layer is not disposed above a portion to which the first bonding wire is connected.
27. The semiconductor device according to claim 24 , further comprising
a second bonding wire connected to the second pad electrode, wherein
the first bonding layer is not disposed above a portion to which the second bonding wire is connected.
28. The semiconductor device according to claim 24 , further comprising
a gate metal lead connected to the second pad electrode.
29. The semiconductor device according to claim 24 , wherein
the first bonding layer comprises an Ag fired layer or a Cu fired layer.