Method of manufacturing a semiconductor device and a semiconductor device
In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
1. A semiconductor device, comprising:
a fin structure extending in a first direction;
an isolation insulating layer from which the fin structure protrudes;
a source/drain epitaxial layer disposed over the fin structure;
a source/drain contact in contact with the source/drain epitaxial layer; and
a gate structure extending in a second direction crossing the first direction and including a gate electrode and a gate cap insulating layer,
wherein in a cross section cutting the fin structure along the first direction, the source/drain contact has a top width greater than a bottom width, and
in a cross section along the first direction, opposite sides of a top of the gate cap insulating layer are recessed such that a top width of the gate cap insulating layer is smaller than a bottom width of the gate cap insulating layer.
2. The semiconductor device of claim 1 , wherein the source/drain contact is in contact with the gate cap insulating layer.
3. The semiconductor device of claim 1 , further comprising a gate sidewall spacer disposed on a sidewall of the gate structure.
4. The semiconductor device of claim 3 , wherein the gate sidewall spacer only partially covers a sidewall of the gate cap insulating layer.
5. The semiconductor device of claim 1 , further comprising a dielectric layer disposed at a side of the gate structure in the first direction and at a side of the source/drain contact in the second direction.
6. The semiconductor device of claim 5 , wherein in a cross section along the first direction, the dielectric layer has a top width greater than a bottom width.
7. The semiconductor device of claim 5 , wherein the dielectric layer includes a first dielectric layer in contact with the source/drain contact and a second dielectric layer disposed on the first dielectric layer and separated from the source/drain contact by the first dielectric layer.
8. The semiconductor device of claim 7 , wherein the second dielectric layer is in contact with the gate cap insulating layer.
9. The semiconductor device of claim 7 , wherein the second dielectric layer comprises a silicon nitride based material.
10. The semiconductor device of claim 9 , wherein the second dielectric layer further comprises GeO.
11. The semiconductor device of claim 7 , wherein the first dielectric layer comprises GeO.
12. A semiconductor device, comprising:
a first FinFET including a first fin structure, a first source/drain epitaxial layer, a first source/drain contact disposed over the first source/drain epitaxial layer;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure, a second source/drain epitaxial layer and a second source/drain contact disposed over the second source/drain epitaxial layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact, wherein:
the first and second fin structures extend in a first direction,
the first FinFET and the second FinFET share a gate structure extending in a second direction crossing the first direction and including a gate electrode layer and a gate cap insulating layer,
in a cross section cutting the first fin structure along the first direction, the first source/drain contact has a funnel shape having a wider top than a body region, and
in a cross section of the first FinFET along the first direction, opposite sides of a top of the gate cap insulating layer are recessed such that a top width of the gate cap insulating layer is smaller than a bottom width of the gate cap insulating layer.
13. The semiconductor device of claim 12 , wherein in a cross section cutting the dielectric layer along the first direction, the dielectric layer has a funnel shape having a wider top than a body region.
14. The semiconductor device of claim 12 , wherein the dielectric layer includes a first dielectric layer in contact with the first and second source/drain contacts and a second dielectric layer disposed on the first dielectric layer.
15. The semiconductor device of claim 14 , wherein the second dielectric layer is in contact with the gate cap insulating layer.
16. The semiconductor device of claim 14 , wherein the second dielectric layer comprises a silicon nitride based material.
17. The semiconductor device of claim 16 , wherein the second dielectric layer further comprises GeO.
18. The semiconductor device of claim 14 , wherein the first dielectric layer comprises GeO.
19. A semiconductor device, comprising:
a first FinFET including a first fin structure, a first gate structure, a first source/drain epitaxial layer, a first source/drain contact disposed over the first source/drain epitaxial layer;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure, a second gate structure, a second source/drain epitaxial layer and a second source/drain contact disposed over the second source/drain epitaxial layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact, wherein:
the first and second fin structures extend in a first direction,
the first and second gate structures extend in a second direction crossing the first direction,
in a cross section cutting the first fin structure along the first direction, the first source/drain contact has a funnel shape having a wider top than a body region, and
in a cross section of the first FinFET along the first direction, opposite sides of a top of a gate cap insulating layer are recessed such that a top width of the gate cap insulating layer is smaller than a bottom width of the gate cap insulating layer.
20. The semiconductor device of claim 19 , wherein the dielectric layer comprises germanium.