Semiconductor device including ferroelectric material, neuromorphic circuit including the semiconductor device, and neuromorphic computing apparatus including the neuromorphic circuit
A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.
1. A neuromorphic circuit comprising:
pre-synaptic neuron circuits;
pre-synaptic lines extending in a first direction from the pre-synaptic neuron circuits;
post synaptic neuron circuits;
post synaptic lines extending from the post synaptic neuron circuits in a second direction crossing the first direction; and
synaptic circuits provided at intersections of the pre-synaptic lines and the post synaptic lines,
the synaptic circuits each including a first transistor including a first channel layer of a first conductivity type, a second transistor having a second channel layer of a second conductivity type, and a third transistor being positioned on at least one of the first transistor and the second transistor on a substrate,
wherein the third transistor includes a third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with a gate insulating film therebetween, the third channel layer including at least one of InGaZnO, InZnO, and InSnZnO, and the gate insulating film including a ferroelectric material comprising at least one of HfO, Hf x Zr 1-x O, and ZrO.
2. The neuromorphic circuit of claim 1 , wherein the first transistor and the second transistor are electrically connected to each other.
3. The neuromorphic circuit of claim 1 , further comprising:
a contact electrode, wherein
the contact electrode electrically connects a drain electrode of the first transistor to a drain electrode of the second transistor.
4. The neuromorphic circuit of claim 3 , wherein a portion of the contact electrode is in contact with the gate electrode of the third transistor.
5. The neuromorphic circuit of claim 1 , wherein a variation of a resistance of the third channel layer according to a signal applied to the gate electrode of the third transistor has symmetry.
6. The neuromorphic circuit of claim 1 , wherein a resistance of the third channel layer according to a signal applied to the gate electrode of the third transistor linearly changes.
7. The neuromorphic circuit of claim 1 , wherein
the ferroelectric material is doped with at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf.
8. The neuromorphic circuit of claim 1 , wherein
the gate electrode of the third transistor is above the gate insulating film, and
the third channel layer is below the gate insulating film.
9. The neuromorphic circuit of claim 1 , wherein
the gate insulating film is a lower gate insulating film that is below the third channel layer,
the third transistor further includes an upper gate insulating film above the third channel layer that includes a ferroelectric material, and
the gate electrode is a lower gate electrode below the lower gate insulating film, and
the third transistor further includes an upper gate electrode above the upper gate insulating film.
10. The neuromorphic circuit of claim 9 , wherein
the lower gate insulating film includes a first polarization state and the upper gate insulating film includes a second polarization state that is different from the first polarization state.
11. The neuromorphic circuit of claim 1 , wherein the first channel layer and the second channel layer each include silicon.
12. A neuromorphic computing apparatus comprising:
an input device;
the neuromorphic circuit of claim 1 , the neuromorphic circuit being configured to store and output specific information using a signal received from the input device; and
a processor configured to process information that is output from the neuromorphic circuit.
13. A neuromorphic circuit comprising:
a synaptic circuit including a semiconductor device;
a pre-synaptic neuron circuit;
a pre-synaptic line connecting the synaptic circuit to the pre-synaptic neuron circuit;
a post-synaptic neuron circuit; and
a post-synaptic line connecting the synaptic circuit to the post-synaptic neuron circuit, wherein
the semiconductor device includes a CMOS circuit including a first transistor of a first conductivity type and a second transistor of a second conductivity type, a third transistor, and a contact electrode,
the third transistor includes a gate electrode, a channel, and a gate insulating film,
the gate insulating film includes a ferroelectric material,
the contact electrode is connected to the gate electrode of the third transistor, a drain of the first transistor, and a drain of the second transistor,
the channel of the third transistor is laterally between a source electrode of the third transistor and a drain electrode of the third transistor such that the channel of the third transistor contacts a sidewall of the source electrode of the third transistor and a sidewall of the drain electrode of the third transistor,
the gate electrode is spaced apart vertically from the channel, does not vertically overlap the source electrode of the third transistor, and does not vertically overlap the drain electrode of the third transistor,
the ferroelectric material includes at least one of HfO, Hf x Zr 1-x O, and ZrO,
the ferroelectric material is doped with at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf, and
the channel of the third transistor includes at least one of InGaZnO, InZnO, and InSnZnO.
14. The neuromorphic circuit of claim 13 , wherein the first transistor and the second transistor are electrically connected to each other.
15. The neuromorphic circuit of claim 13 , wherein a portion of the contact electrode is in contact with the gate electrode of the third transistor.
16. The neuromorphic circuit of claim 13 , wherein a variation of a resistance of the channel of the third transistor according to a signal applied to the gate electrode of the third transistor has symmetry.
17. The neuromorphic circuit of claim 13 , wherein a resistance of the channel of the third transistor according to a signal applied to the gate electrode of the third transistor linearly changes.
18. The neuromorphic circuit of claim 13 , wherein
the gate electrode of the third transistor is above the gate insulating film, and
the channel of the third transistor is below the gate insulating film.
19. The neuromorphic circuit of claim 13 , wherein
the first transistor includes a first channel layer,
the second transistor includes a second channel layer, and
the first channel layer and the second channel layer each include silicon.
20. A neuromorphic computing apparatus comprising:
an input device;
the neuromorphic circuit of claim 13 , the neuromorphic circuit being configured to store and output specific information using a signal received from the input device; and
a processor configured to process information that is output from the neuromorphic circuit.