Radio frequency transmitter with dynamic impedance matching for high linearity
Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.
1. A transmitter circuit configured to generate a signal for wireless transmission, the transmitter circuit comprising:
a switched-capacitor array comprising a plurality of unit cells, wherein:
each of the plurality of unit cells comprises a capacitor; and
for at least a first unit cell of the plurality of unit cells, a terminal of the capacitor of the first unit cell is configured to be selectively coupled to a reference potential node, to a power supply rail, and to a common-mode voltage node,
wherein the first unit cell comprises:
a first switch configured to selectively couple the terminal of the capacitor of the first unit cell to the reference potential node;
a second switch configured to selectively couple the terminal of the capacitor of the first unit cell to the power supply rail; and
a third switch configured to selectively couple the terminal of the capacitor of the first unit cell to the common-mode voltage node.
2. The transmitter circuit of claim 1 , wherein the first unit cell is capable of being configured in a first state or in a second state, the second state being different from the first state.
3. The transmitter circuit of claim 2 , wherein an output impedance of the first unit cell in the first state is equal to an output impedance of the first unit cell in the second state.
4. The transmitter circuit of claim 2 , wherein:
the first switch and the second switch are configured to be open during the second state; and
the third switch is configured to be closed during the second state.
5. The transmitter circuit of claim 4 , wherein:
the first switch and the second switch are configured to be selectively closed during the first state based on a signal input to the switched-capacitor array; and
the third switch is configured to be open during the first state.
6. The transmitter circuit of claim 1 , wherein:
the third switch comprises a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor;
a drain of the PMOS transistor and a drain of the NMOS transistor are coupled to the terminal of the capacitor of the first unit cell; and
a source of the PMOS transistor and a source of the NMOS transistor are coupled to the common-mode voltage node.
7. The transmitter circuit of claim 1 , wherein a bias voltage of the common-mode voltage node is half of a supply voltage of the power supply rail.
8. The transmitter circuit of claim 1 , wherein:
the first unit cell is clocked by a signal having a first phase or a second phase; and
at least one of the first phase or the second phase is based on a multi-phase architecture.
9. The transmitter circuit of claim 8 , wherein the multi-phase architecture comprises a diamond architecture, a hexagon architecture, an octagon architecture, or a decagon architecture.
10. A wireless communication device comprising:
a switched-capacitor array configured to generate a signal at a transmission frequency and comprising a plurality of unit cells, wherein:
each of the plurality of unit cells comprises a capacitor and is capable of being configured in a first state or in a second state, the second state being different from the first state; and
for at least a first unit cell of the plurality of unit cells, the first unit cell is configured to couple a terminal of the capacitor of the first unit cell to a common-mode voltage node during the second state; and
an antenna configured to output signals for wireless transmission at the transmission frequency,
wherein the first unit cell is further configured to selectively couple the terminal of the capacitor to a reference potential node or to a power supply rail during the first state, and
wherein the first unit cell comprises:
a first switch configured to selectively couple the terminal of the capacitor of the first unit cell to the reference potential node;
a second switch configured to selectively couple the terminal of the capacitor of the first unit cell to the power supply rail; and
a third switch configured to selectively couple the terminal of the capacitor of the first unit cell to the common-mode voltage node.
11. The wireless communication device of claim 10 , wherein:
the first switch and the second switch are configured to be open during the second state; and
the third switch is configured to be closed during the second state.
12. The wireless communication device of claim 11 , wherein:
the first switch and the second switch are configured to be selectively closed during the first state based on a signal input to the switched-capacitor array; and
the third switch is configured to be open during the first state.
13. The wireless communication device of claim 10 , wherein:
the third switch comprises a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor;
a drain of the PMOS transistor and a drain of the NMOS transistor are coupled to the terminal of the capacitor of the first unit cell; and
a source of the PMOS transistor and a source of the NMOS transistor are coupled to the common-mode voltage node.
14. The wireless communication device of claim 10 , wherein an output impedance of the first unit cell in the first state is equal to an output impedance of the first unit cell in the second state.
15. The wireless communication device of claim 10 , wherein a bias voltage of the common-mode voltage node is half of a supply voltage of a power supply rail.
16. The wireless communication device of claim 10 , wherein:
the first unit cell is clocked by a signal having a first phase or a second phase; and
at least one of the first phase or the second phase is based on a multi-phase architecture.
17. The wireless communication device of claim 16 , wherein the multi-phase architecture comprises a diamond architecture, a hexagon architecture, an octagon architecture, or a decagon architecture.
18. The wireless communication device of claim 10 , wherein the antenna is coupled to an output of the switched-capacitor array and wherein another terminal of the capacitor of the first unit cell is coupled to the output of the switched-capacitor array.
19. The wireless communication device of claim 10 , wherein the first state comprises an active state and the second state comprises a sleep state.
20. A wireless communication device, comprising:
a switched-capacitor array configured to generate a signal at a transmission frequency and comprising a plurality of unit cells, wherein:
each of the plurality of unit cells comprises a capacitor and is capable of being configured in a first state or in a second state, the second state being different from the first state; and
for at least a first unit cell of the plurality of unit cells, the first unit cell is configured to couple a terminal of the capacitor of the first unit cell to a common-mode voltage node during the second state;
an antenna configured to output signals for wireless transmission at the transmission frequency, wherein the antenna is coupled to an output of the switched-capacitor array and wherein another terminal of the capacitor of the first unit cell is coupled to the output of the switched-capacitor array; and
a transformer including a primary winding coupled to the output of the switched-capacitor array and including a secondary winding coupled to the antenna.
21. The wireless communication device of claim 20 , wherein an output impedance of the first unit cell in the first state is equal to an output impedance of the first unit cell in the second state.
22. The wireless communication device of claim 20 , wherein a bias voltage of the common-mode voltage node is half of a supply voltage of a power supply rail.
23. The wireless communication device of claim 20 , wherein:
the first unit cell is clocked by a signal having a first phase or a second phase; and
at least one of the first phase or the second phase is based on a multi-phase architecture.