High performance interconnect
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
1. An apparatus comprising:
a port to couple to a device over a link, wherein the port comprises:
protocol circuitry to:
implement a cache coherent interconnect protocol on the link; and
generate a flit with a format defined in accordance with the cache coherent interconnect protocol, wherein the flit comprises at least three slots and a cyclic redundancy check (CRC) code based on the format, a first one of the three slots is to carry at least a portion of a first message, and a second one of the three slots is to carry at least a portion of a different second message; and
a transmitter to send the flit to another device over the link.
2. The apparatus of claim 1 , wherein each of the at least three slots has a respective defined size according to the format.
3. The apparatus of claim 1 , wherein the portion of the respective message comprises header data of the message.
4. The apparatus of claim 1 , wherein the portion of the respective message comprises payload data of the message.
5. The apparatus of claim 4 , wherein one of the at least three slots is capable of carrying both header data and payload data of the message.
6. The apparatus of claim 1 , wherein the format defines that the flit further comprises a credit return field.
7. The apparatus of claim 1 , wherein the format defines that the flit further comprises a type field to indicate a type of the flit from a plurality of types.
8. The apparatus of claim 7 , wherein the plurality of types comprises a link layer control flit or a protocol flit corresponding to the cache coherent interconnect protocol.
9. The apparatus of claim 1 , wherein the format defines that the flit further comprises an OpCode field.
10. The apparatus of claim 1 , wherein the format defines that the flit further comprises an acknowledgement field.
11. The apparatus of claim 1 , wherein the CRC code comprises a 16-bit CRC code.
12. A method comprising:
identifying a set of messages to be sent on a link from a first device to a second device, wherein the link couples the first device to the second device and the link is compliant with a cache coherent interconnect protocol;
generating a set of flits according to the cache coherent interconnect protocol, wherein each flit in the set of flits comprises a plurality of slots, each of the slots is to carry at least a portion of a respective message in the set of messages, a first one of the plurality of slots in a first one of the set of flits is to carry a portion of a first one of the set of messages, and a second one of the plurality of slots in the first flit is to carry a portion of a second one of the set of messages; and
sending the set of messages from the first device to the second device in the set of flits.
13. The method of claim 12 , further comprising calculating a respective cyclic redundancy check (CRC) value for each one of the set of flits, wherein each of the set of flits comprises a CRC field to include the corresponding calculated CRC value.
14. The method of claim 12 , wherein each of the set of flits further comprises a respective credit return field, and the method further comprises:
identify a credit return; and
set a value in the credit return field of one of the set of flits to identify the credit return.
15. The method of claim 12 , wherein the portion of the first message comprises one or both of header data of the first message or payload data of the first message.
16. A system comprising:
a first device; and
a second device coupled to the first device by a link, wherein the link is compliant with a cache coherent interconnect protocol, and the second device comprises protocol circuitry to support the interconnect protocol and the protocol circuitry is to:
generate a flit with a format defined in accordance with the interconnect protocol, wherein the flit comprises at least three slots and a cyclic redundancy check (CRC) code based on the format, and each of the three slots is capable of carrying at least a portion of a different message; and
send the flit to another device over the link.
17. The system of claim 16 , wherein the format further defines that the flit further comprises an acknowledgement field, a credit return field, a type field, and an opcode field.
18. The system of claim 16 , wherein the first device comprises a first processor device and the second device comprises a second processor device.
19. The system of claim 16 , wherein one of the first device or the second device comprises an accelerator device.
20. The system of claim 16 , wherein one of the first device or the second device comprises a memory device.