Scan circuit and display apparatus
A scan circuit is provided. The scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to one or more rows of subpixels. A respective scan unit includes a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit. A pull-up node is coupled to the second subcircuit, the third subcircuit, and the fourth subcircuit. A pull-down node is coupled to the second subcircuit, the third subcircuit. The denoising subcircuit is coupled to a pull-up node and the input terminal, or coupled between a third power supply voltage terminal and the pull-down control node.
1. A scan circuit, comprising a plurality of stages, wherein a respective stage of the scan circuit comprises a respective scan unit configured to provide a control signal to one or more rows of subpixels;
wherein the respective scan unit comprises a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit, and a denoising subcircuit;
wherein a pull-up node is coupled to the second subcircuit, the third subcircuit, and the fourth subcircuit;
a pull-down node is coupled to the second subcircuit, the third subcircuit;
the first subcircuit is configured to receive an input signal and a first power supply voltage signal and configured to control a potential level at the pull-up node based on the input signal received from an input terminal;
the second subcircuit is configured to receive a first voltage signal and a third power supply voltage signal, and configured to control potential levels at the pull-down node based on the first voltage signal and the potential level at the pull-up node;
the third subcircuit is configured to receive the third power supply voltage signal, and configured to pull down potential levels at an output terminal and the pull-up node based on the potential level at the pull-down node;
the fourth subcircuit is configured to receive a first clock signal and output the control signal, and configured to output the control signal based on the first clock signal and the potential level at the pull-up node; and
the denoising subcircuit is directly coupled to the pull-up node and the input terminal.
2. The scan circuit of claim 1 , wherein the first subcircuit and the denoising subcircuit together are configured to pull up a potential level at the pull-up node based on the input signal received from the input terminal.
3. The scan circuit of claim 2 , wherein the first subcircuit and the denoising subcircuit together are configured to reset a potential level at the pull-up node based on a reset signal received from a reset terminal.
4. The scan circuit of claim 1 , wherein the denoising subcircuit comprises a first denoising transistor and a third denoising transistor;
the first denoising transistor is coupled between the input terminal and the third denoising transistor; and
the third denoising transistor is coupled between the pull-up node and second electrodes of an input transistor controlled by the input signal and a reset transistor controlled by a reset signal.
5. The scan circuit of claim 4 , wherein a gate electrode and a first electrode of the first denoising transistor are coupled to the input terminal;
a second electrode of the first denoising transistor is coupled to a gate electrode of the third denoising transistor;
a first electrode of the third denoising transistor is coupled to second electrodes of the input transistor and the reset transistor; and
a second electrode of the third denoising transistor is coupled to the pull-up node.
6. The scan circuit of claim 4 , wherein the denoising subcircuit further comprises a second denoising transistor; and
the second denoising transistor is coupled between a reset terminal and the third denoising transistor.
7. The scan circuit of claim 6 , wherein a gate electrode and a first electrode of the second denoising transistor are coupled to the reset terminal; and
a second electrode of the second denoising transistor is coupled to a second electrode of the first denoising transistor and a gate electrode of the third denoising transistor.
8. The scan circuit of claim 1 , wherein the denoising subcircuit comprises a fourth denoising transistor; and
the fourth denoising transistor is coupled between the pull-up node and an input transistor controlled by the input signal.
9. The scan circuit of claim 8 , wherein a gate electrode of the fourth denoising transistor is coupled to the input terminal;
a first electrode of the fourth denoising transistor is coupled to a second electrode of the input transistor; and
a second electrode of the fourth denoising transistor is coupled to the pull-up node.
10. The scan circuit of claim 8 , wherein the denoising subcircuit further comprises a fifth denoising transistor;
a gate electrode of the fifth denoising transistor is coupled to a reset terminal;
a first electrode of the fifth denoising transistor is coupled to a second electrode of a reset transistor controlled by a reset signal; and
a second electrode of the fifth denoising transistor is coupled to the pull-up node.
11. A display apparatus, comprising the scan circuit of claim 1 , and a display panel comprising a plurality of light emitting elements.
12. A scan circuit, comprising a plurality of stages, wherein a respective stage of the scan circuit comprises a respective scan unit configured to provide a control signal to one or more rows of subpixels;
wherein the respective scan unit comprises a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit, and a denoising subcircuit;
wherein a pull-up node is coupled to the second subcircuit, the third subcircuit, and the fourth subcircuit;
a pull-down node is coupled to the second subcircuit, the third subcircuit;
the first subcircuit is configured to receive an input signal and a first power supply voltage signal and configured to control a potential level at the pull-up node based on the input signal received from an input terminal;
the second subcircuit is configured to receive a first voltage signal and a third power supply voltage signal, and configured to control potential levels at the pull-down node based on the first voltage signal and the potential level at the pull-up node;
the third subcircuit is configured to receive the third power supply voltage signal, and configured to pull down potential levels at an output terminal and the pull-up node based on the potential level at the pull-down node;
the fourth subcircuit is configured to receive a first clock signal and output the control signal, and configured to output the control signal based on the first clock signal and the potential level at the pull-up node; and
the denoising circuit is directly coupled between a third power supply voltage terminal and a pull-down control node configured to control the potential level at the pull-down node.
13. The scan circuit of claim 12 , wherein the third power supply voltage terminal is configured to provide a third power supply voltage signal at a second level; and
the denoising subcircuit is controlled by a potential level at the pull-down control node to pull down the potential level at the output terminal or the pull-up node based on the potential level at the pull-down control node.
14. The scan circuit of claim 12 , wherein the denoising subcircuit comprises a sixth denoising transistor;
a gate electrode of the sixth denoising transistor is coupled to the pull-down control node;
a first electrode of the sixth denoising transistor is coupled to the third power supply voltage terminal; and
a second electrode of the sixth denoising transistor is coupled to the pull-up node.
15. The scan circuit of claim 12 , wherein the denoising subcircuit comprises a seventh denoising transistor;
a gate electrode of the seventh denoising transistor is coupled to the pull-down control node;
a first electrode of the seventh denoising transistor is coupled to the third power supply voltage terminal; and
a second electrode of the seventh denoising transistor is coupled to the output terminal.
16. The scan circuit of claim 12 , wherein the denoising subcircuit comprises a sixth denoising transistor and a seventh denoising transistor;
a gate electrode of the sixth denoising transistor is coupled to the pull-down control node;
a first electrode of the sixth denoising transistor is coupled to the third power supply voltage terminal;
a second electrode of the sixth denoising transistor is coupled to the pull-up node;
a gate electrode of the seventh denoising transistor is coupled to the pull-down control node;
a first electrode of the seventh denoising transistor is coupled to the third power supply voltage terminal; and
a second electrode of the seventh denoising transistor is coupled to the output terminal.
17. The scan circuit of claim 12 , wherein the first subcircuit comprises a first transistor and a second transistor;
the first transistor is coupled between a first power supply voltage terminal and the pull-up node;
a gate electrode of the first transistor is coupled to the input terminal;
a first electrode of the first transistor is coupled to the first power supply voltage terminal;
a second electrode of the first transistor is coupled to the pull-up node;
the second transistor is coupled between a second power supply voltage terminal and the pull-up node;
a gate electrode of the second transistor is coupled to a reset terminal;
a first electrode of the second transistor is coupled to the second power supply voltage terminal; and
a second electrode of the second transistor is coupled to the pull-up node.
18. The scan circuit of claim 12 , wherein the second subcircuit comprises a fifth transistor, a sixth transistor, an eighth transistor, and a ninth transistor;
the ninth transistor is coupled between a first voltage signal terminal and a pull-down control node;
a gate electrode and a first electrode of the ninth transistor are coupled to the first voltage signal terminal;
a second electrode of the ninth transistor is coupled to the pull-down control node;
the fifth transistor is coupled between the first voltage signal terminal and a pull-down node;
a gate electrode of the fifth transistor is coupled to the pull-down control node;
a first electrode of the fifth transistor is coupled to the first voltage signal terminal;
a second electrode of the fifth transistor is coupled to the pull-down node;
the sixth transistor is coupled between the pull-down node and a third power supply voltage terminal;
a gate electrode of the sixth transistor is coupled to the pull-up node;
a first electrode of the sixth transistor is coupled to the third power supply voltage terminal;
a second electrode of the sixth transistor is coupled to the pull-down node;
the eighth transistor is coupled between the pull-down control node and the third power supply voltage terminal;
a gate electrode of the eighth transistor is coupled to the pull-up node;
a first electrode of the eighth transistor is coupled to the third power supply voltage terminal; and
a second electrode of the eighth transistor is coupled to the pull-down control node.
19. The scan circuit of claim 12 , wherein the third subcircuit comprises a tenth transistor and an eleventh transistor;
the tenth transistor is coupled between the pull-up node and a third power supply voltage terminal;
a gate electrode of the tenth transistor is coupled to the pull-down node;
a first electrode of the tenth transistor is coupled to the third power supply voltage terminal;
a second electrode of the tenth transistor is coupled to the pull-up node;
the eleventh transistor is coupled between the output terminal and the third power supply voltage terminal;
a gate electrode of the eleventh transistor is coupled to the pull-down node;
a first electrode of the eleventh transistor is coupled to the third power supply voltage terminal; and
a second electrode of the eleventh transistor is coupled to the output terminal.
20. The scan circuit of claim 12 , wherein the fourth subcircuit comprises a third transistor, a fourth transistor, a seventh transistor, and a capacitor;
the third transistor is coupled between the output terminal and a first clock signal terminal;
a gate electrode of the third transistor is coupled to the pull-up node;
a first electrode of the third transistor is coupled to the first clock signal terminal;
a second electrode of the third transistor is coupled to the output terminal;
the fourth transistor is coupled between the pull-up node and a third power supply voltage terminal;
a gate electrode of the fourth transistor is coupled to a start signal terminal;
a first electrode of the fourth transistor is coupled to the third power supply voltage terminal;
a second electrode of the fourth transistor is coupled to the pull-up node;
the seventh transistor is coupled between the output terminal and the third power supply voltage terminal;
a gate electrode of the seventh transistor is coupled to a second voltage signal terminal;
a first electrode of the seventh transistor is coupled to the third power supply voltage terminal;
a second electrode of the seventh transistor is coupled to the output terminal;
the capacitor is coupled between the output terminal and the pull-up node;
a first electrode of the capacitor is coupled to the pull-up node; and
a second electrode of the capacitor is coupled to the output terminal;
wherein, during a blanking period, a second voltage signal input from the second voltage signal terminal is at a first level, turning on the seventh transistor; and
the third power supply voltage signal provided to a third power supply voltage terminal at a second level passed through the seventh transistor to the output terminal, resetting the scan circuit.