Sense amplifier, method for driving sense amplifier, and memory
A sense amplifier includes an amplifying circuit and a voltage equalizing circuit. The amplifying circuit includes: a first P-type transistor, having a first terminal connected to a third node, a second terminal connected to a first node, and a gate connected to a first bit line; a second P-type transistor, having a first terminal connected to the third node, a second terminal connected to a second node, and a gate connected to a second bit line; a first N-type transistor, having a first terminal connected to the first node, a second terminal connected to a fourth node, and a gate connected to the first bit line; a second N-type transistor, having a first terminal connected to the second node, a second terminal connected to the fourth node, a gate connected to the second bit line. The voltage equalizing circuit is connected between the first node and the second node.
1. A sense amplifier, comprising:
an amplifying circuit, comprising:
a first P-type transistor, having a first terminal connected to a third node, a second terminal connected to a first node, and a gate connected to a first bit line;
a second P-type transistor, having a first terminal connected to the third node, a second terminal connected to a second node, and a gate connected to a second bit line;
a first N-type transistor, having a first terminal connected to the first node, a second terminal connected to a fourth node, and a gate connected to the first bit line; and
a second N-type transistor, having a first terminal connected to the second node, a second terminal connected to the fourth node, and a gate connected to the second bit line; and
a voltage equalizing circuit, connected between the first node and the second node, and configured to connect the first node and the second node in a charge sharing stage.
2. The sense amplifier of claim 1 , wherein the voltage equalizing circuit is further connected to a pre-charging voltage end, and the voltage equalizing circuit is further configured to transmit a pre-charging voltage at the pre-charging voltage end to the first node and the second node in a pre-charging stage.
3. The sense amplifier of claim 2 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end;
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to a pre-charging control end; and
a third transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the second node, and a gate connected to the pre-charging control end.
4. The sense amplifier of claim 2 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end;
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to the first control signal end; and
a third transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the second node, and a gate connected to the first control signal end.
5. The sense amplifier of claim 2 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end; and
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to a pre-charging control end.
6. The sense amplifier of claim 2 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end; and
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to the first control signal end.
7. The sense amplifier of claim 1 , further comprising:
an offset cancelling circuit, connected to the first bit line, the second bit line, the first node, the second node and a second control signal end, and configured to respond to a signal of the second control signal end to connect the first bit line and the first node, and respond to the signal of the second control signal end to connect the second bit line and the second node; and
an isolation circuit, connected to the first bit line, the second bit line, the first node, the second node and a third control signal end, and configured to respond to a signal of the third control signal end to connect the first bit line and the second node, and respond to the signal of the third control signal end to connect the second bit line and the first node.
8. The sense amplifier of claim 7 , wherein the offset cancelling circuit comprises:
a fourth transistor, having a first terminal connected to the first node, a second terminal connected to the first bit line, and a gate connected to the second control signal end; and
a fifth transistor, having a first terminal connected to the second node, a second terminal connected to the second bit line, and a gate connected to the second control signal end.
9. The sense amplifier of claim 7 , wherein the isolation circuit comprises:
a sixth transistor, having a first terminal connected to the first bit line, a second terminal connected to the second node, and a gate connected to the third control signal end;
a seventh transistor, having a first terminal connected to the second bit line, a second terminal connected to the first node, and a gate connected to the third control signal end.
10. The sense amplifier of claim 8 , wherein the fourth transistor and the fifth transistor are both N-type transistors, or the fourth transistor and the fifth transistor are both P-type transistors.
11. The sense amplifier of claim 9 , wherein the sixth transistor and the seventh transistor are both N-type transistors, or the sixth transistor and the seventh transistor are both P-type transistors.
12. A method for driving a sense amplifier of claim 7 , the method comprising: when the voltage equalizing circuit is connected to a pre-charging voltage end,
in a pre-charging stage, providing, by the voltage equalizing circuit, a preset voltage of the pre-charging voltage end to the first node and the second node; connecting, by the offset cancelling circuit, the first node and the first bit line, and connecting the second node and the second bit line; and connecting, by the isolation circuit, the first node and the second bit line, connecting the second node and the first bit line, and providing the preset voltage to the third node and the fourth node;
in an offset cancelling stage, connecting, by the offset cancelling circuit, the first node and the first bit line, connecting the second node and the second bit line, providing a first level to the third node, and providing a second level to the fourth node;
in the charge sharing stage, connecting, by the voltage equalizing circuit, the first node and the second node, and providing the preset voltage to the third node and the fourth node; and
in a signal amplification stage, connecting, by the isolation circuit, the first node and the second bit line, connecting the second node and the first bit line, providing a first level to the third node, and providing a second level to the fourth node.
13. The method for driving a sense amplifier of claim 12 , further comprising:
in a charge cancelling stage, writing the preset voltage into the third node and the fourth node, the charge cancelling stage being between the offset cancelling stage and the charge sharing stage.
14. The method for driving a sense amplifier of claim 12 , further comprising:
in an amplification preparation stage, connecting, by the isolation circuit, the first node and the second bit line, and connecting the second node and the first bit line, the amplification preparation stage being between the charge sharing stage and the signal amplification stage.
15. A memory, comprising a sense amplifier, wherein the sense amplifier comprises:
an amplifying circuit, comprising:
a first P-type transistor, having a first terminal connected to a third node, a second terminal connected to a first node, and a gate connected to a first bit line;
a second P-type transistor, having a first terminal connected to the third node, a second terminal connected to a second node, and a gate connected to a second bit line;
a first N-type transistor, having a first terminal connected to the first node, a second terminal connected to a fourth node, and a gate connected to the first bit line; and
a second N-type transistor, having a first terminal connected to the second node, a second terminal connected to the fourth node, and a gate connected to the second bit line; and
a voltage equalizing circuit, connected between the first node and the second node, and configured to connect the first node and the second node in a charge sharing stage.
16. The memory of claim 15 , wherein the voltage equalizing circuit is further connected to a pre-charging voltage end, and the voltage equalizing circuit is further configured to transmit a pre-charging voltage at the pre-charging voltage end to the first node and the second node in a pre-charging stage.
17. The memory of claim 16 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end;
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to a pre-charging control end; and
a third transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the second node, and a gate connected to the pre-charging control end.
18. The memory of claim 16 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end;
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to the first control signal end; and
a third transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the second node, and a gate connected to the first control signal end.
19. The memory of claim 16 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end; and
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to a pre-charging control end.
20. The memory of claim 16 , wherein the voltage equalizing circuit comprises:
a first transistor, having a first terminal connected to the first node, a second terminal connected to the second node, and a gate connected to a first control signal end; and
a second transistor, having a first terminal connected to the pre-charging voltage end, a second terminal connected to the first node, and a gate connected to the first control signal end.