Seal ring structures
Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a circuit region and a seal ring region surrounding the circuit region. The seal ring region includes a first active region extending lengthwise in a first direction and a first gate structure disposed on the first active region. The first gate structure extends lengthwise in a second direction that is tilted from the first direction. The first direction and the second direction form a tilted angle therebetween.
1. An integrated circuit (IC) chip, comprising:
a circuit region; and
a seal ring region surrounding the circuit region, the seal ring region comprising:
a first active region extending lengthwise in a first direction, and
a first gate structure disposed on the first active region, the first gate structure extending lengthwise in a second direction that is tilted from the first direction, wherein the first direction and the second direction form a tilted angle therebetween, and wherein the titled angle is non-orthogonal.
2. The IC chip of claim 1 , wherein the tilted angle formed between the first direction and the second direction is about 45 degrees.
3. The IC chip of claim 1 , wherein the first gate structure extends lengthwise parallel to an edge of the IC chip.
4. The IC chip of claim 3 , wherein the first active region extends lengthwise in a 45-degree angle with respect to the edge of the IC chip.
5. The IC chip of claim 1 , wherein a perimeter of the first gate structure is within a perimeter of the first active region.
6. The IC chip of claim 1 , wherein the first active region includes a first edge and a second edge that is opposing the first edge, and wherein the first edge is distant from the first gate structure for a first distance and the second edge is distant from the first gate structure for a second distance that is larger than the first distance.
7. The IC chip of claim 6 , wherein a ratio between the second distance and the first distance ranges from about 1:1 to about 8:1.
8. The IC chip of claim 1 , wherein the circuit region comprising:
a second active region, and
a second gate structure disposed on the second active region,
wherein a ratio between a width of the first active region and a width of the second active region ranges from about 3:1 to about 15:1.
9. The IC chip of claim 8 , wherein the second active region includes a plurality of channel members vertically stacked, each of the channel members is wrapped around by the second gate structure, and the first active region includes a stack of alternating first semiconductor layers and second semiconductor layers.
10. The IC chip of claim 1 , wherein the first active region and the first gate structure is within a corner stress release (CSR) area of the seal ring region.
11. An integrated circuit (IC) chip, comprising:
a substrate;
an active region protruding from the substrate, wherein the active region includes a stack of alternating first semiconductor layers and second semiconductor layers and two source/drain features sandwiching the stack; and
a gate structure disposed on a top surface of the stack, wherein in a top view a contour of a top surface of an entirety of the gate structure is within a contour of a top surface of the active region.
12. The IC chip of claim 11 , wherein in the top view the contour of the gate structure is within a contour of the stack.
13. The IC chip of claim 11 , wherein the two source/drain features have different widths.
14. The IC chip of claim 11 , wherein the active region has two opposing edges, and the two opposing edges have different distances to the gate structure.
15. The IC chip of claim 11 , further comprising:
a source/drain contact disposed on a first of the two source/drain features, wherein there is no other source/drain contact disposed on a second of the two source/drain features.
16. The IC chip of claim 11 , wherein a lengthwise direction of the active region and a lengthwise direction of the gate structure form a 45-degree angle.
17. A corner stress release (CSR) structure, comprising:
a semiconductor fin of alternating first semiconductor layers and second semiconductor layers that are vertically stacked;
a first epitaxial feature;
a second epitaxial feature, wherein the first and second epitaxial features sandwich the semiconductor fin;
a dielectric fin adjacent the second epitaxial feature; and
a gate structure disposed on the semiconductor fin,
wherein the semiconductor fin extends lengthwise in a first direction, the gate structure extends lengthwise in a second direction that is different from the first direction, the first and second directions form a tilted angle that is non-orthogonal.
18. The CSR structure of claim 17 , wherein the tilted angle is about 45 degrees.
19. The CSR structure of claim 17 , wherein the second epitaxial feature has a larger width than the first epitaxial feature.
20. The CSR structure of claim 17 , further comprising:
a contact feature landing on the second epitaxial feature, wherein the contact feature partially covers a top surface of the dielectric fin.