Gate-all-around integrated circuit structures having nanowires with tight vertical spacing
Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.
1. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires comprising silicon and carbon, wherein a vertical spacing between vertically adjacent nanowires is less than 6 nanometers;
a gate stack around the vertical arrangement of horizontal nanowires, the gate stack having a bottommost surface beneath the vertical arrangement of horizontal nanowires;
a first source or drain structure at a first end of the vertical arrangement of horizontal nanowires, the first source or drain structure having a bottommost surface above the bottommost surface of the gate stack; and
a second source or drain structure at a second end of the vertical arrangement of horizontal nanowires, the second source or drain structure having a bottommost surface above the bottommost surface of the gate stack.
2. The integrated circuit structure of claim 1 , wherein the vertical arrangement of horizontal nanowires is above a fin.
3. The integrated circuit structure of claim 2 , wherein a vertical spacing between the fin and a bottommost nanowire of the vertical arrangement of horizontal nanowires is greater than the vertical spacing between vertically adjacent nanowires.
4. The integrated circuit structure of claim 2 , wherein the fin comprises a portion of a bulk silicon substrate.
5. The integrated circuit structure of claim 1 , wherein the first and second source or drain structures are first and second epitaxial source or drain structures.
6. The integrated circuit structure of claim 5 , wherein the first and second epitaxial source or drain structures comprise silicon and germanium.
7. The integrated circuit structure of claim 5 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.
8. The integrated circuit structure of claim 5 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.
9. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
10. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires comprising silicon and carbon;
a gate stack around the vertical arrangement of horizontal nanowires, the gate stack having a bottommost surface beneath the vertical arrangement of horizontal nanowires;
a first source or drain structure at a first end of the vertical arrangement of horizontal nanowires, the first source or drain structure having a bottommost surface above the bottommost surface of the gate stack; and
a second source or drain structure at a second end of the vertical arrangement of horizontal nanowires, the second source or drain structure having a bottommost surface above the bottommost surface of the gate stack.
11. The integrated circuit structure of claim 10 , wherein the vertical arrangement of horizontal nanowires is above a fin.
12. The integrated circuit structure of claim 11 , wherein a vertical spacing between the fin and a bottommost nanowire of the vertical arrangement of horizontal nanowires is greater than a vertical spacing between vertically adjacent nanowires.
13. The integrated circuit structure of claim 11 , wherein the fin comprises a portion of a bulk silicon substrate.
14. The integrated circuit structure of claim 10 , wherein the first and second source or drain structures are first and second epitaxial source or drain structures.
15. The integrated circuit structure of claim 14 , wherein the first and second epitaxial source or drain structures comprise silicon and germanium.
16. The integrated circuit structure of claim 14 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.
17. The integrated circuit structure of claim 14 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.
18. The integrated circuit structure of claim 10 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
19. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires comprising silicon and carbon, wherein a vertical spacing between vertically adjacent nanowires is less than 6 nanometers;
a gate stack around the vertical arrangement of horizontal nanowires, the gate stack having a bottommost surface beneath the vertical arrangement of horizontal nanowires;
a first source or drain structure at a first end of the vertical arrangement of horizontal nanowires, the first source or drain structure having a bottommost surface above the bottommost surface of the gate stack; and
a second source or drain structure at a second end of the vertical arrangement of horizontal nanowires, the second source or drain structure having a bottommost surface above the bottommost surface of the gate stack.
20. The computing device of claim 19 , wherein the component is a packaged integrated circuit die.