Variable resolution digital equalization
A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
1. An integrated circuit, comprising:
an interface to be coupled to receive a signal that is conveyed via a signal channel, the signal channel to attenuate the signal by an attenuation amount as the signal is conveyed by the signal channel;
an analog-to-digital converter (ADC) to receive the signal via the interface;
adjustable resolution equalization circuitry to receive, from the ADC, a first digital number representing the received signal and to produce a second digital number based at least in part on a digital finite impulse response filtering of a plurality of digital numbers previously received from the ADC; and
control circuitry to determine a resolution of the equalization circuitry based on the attenuation amount.
2. The integrated circuit of claim 1 , wherein the resolution of the equalization is based at least in part on link performance.
3. The integrated circuit of claim 1 , wherein a number of taps that are used to implement the digital finite impulse response filtering is based on the attenuation amount.
4. The integrated circuit of claim 1 , wherein the ADC is configurable to have a plurality of resolutions.
5. The integrated circuit of claim 4 , wherein the ADC is to operate, at least in part, as a successive approximation type ADC.
6. The integrated circuit of claim 4 , wherein the control circuitry adjusts a number of comparisons performed by the ADC per digital number produced.
7. The integrated circuit of claim 4 , wherein the ADC is to operate, at least in part, as a flash type ADC.
8. An integrated circuit to receive a signal from a channel that distorts and attenuates a transmitted signal corresponding to an attenuation indicator, comprising:
an analog-to-digital converter (ADC) to convert the signal from an analog parameter to a first time series of digital values;
adjustable resolution equalization circuitry to receive the first time series of digital values and to produce a second variable resolution time series of digital values based at least in part on a digital finite impulse response filtering of the first time series of digital values; and
control circuitry to, based on the attenuation indicator, determine a resolution of the digital finite impulse response filtering calculations.
9. The integrated circuit of claim 8 , wherein the resolution of the equalization is further based at least in part on link performance.
10. The integrated circuit of claim 9 , wherein a number of taps that are used to implement the digital finite impulse response filtering is based on the attenuation indicator.
11. The integrated circuit of claim 8 , wherein the ADC is configurable to have a plurality of resolutions.
12. The integrated circuit of claim 11 , wherein the ADC is to operate, at least in part, as a successive approximation type ADC.
13. The integrated circuit of claim 11 , wherein the control circuitry adjusts a number of comparisons performed by the ADC per digital number produced.
14. The integrated circuit of claim 11 , wherein the ADC is to operate, at least in part, as a flash type ADC.
15. A method of producing a digital time series representation of a signal attenuated by a channel, comprising:
receiving an attenuation indicator corresponding to an attenuation of the channel;
an analog-to-digital converter (ADC) that receives the signal attenuated by the channel and produces a first time series of digital values based on the signal attenuated by the channel; and
based on the attenuation indicator, selecting a processing resolution for adjustable resolution equalization circuitry that receives a first time series of digital values and produces a second time series of digital values based at least in part of a digital finite impulse response filtering of a portion of the first time series of digital values already received from the ADC.
16. The method of claim 15 , wherein the processing resolution for the adjustable resolution equalization circuitry is further based at least in part on link performance.
17. The method of claim 15 , wherein a number of taps that are used to implement the digital finite impulse response filtering is based on the attenuation indicator.
18. The method of claim 15 , wherein the ADC is configurable to have a plurality of resolutions.
19. The method of claim 15 , wherein the ADC is operating, when producing the first time series of digital values, at least in part as a successive approximation type ADC.
20. The method of claim 15 , further comprising:
adjusting a number of comparisons performed by the ADC per digital number produced.