Semiconductor structure and formation method thereof
A semiconductor structure comprises: a substrate; a first transistor including a first gate located in the substrate and a first terminal located on a surface of the substrate, the first terminal being configured to be connected to a first-type memory cell; and a second transistor including a second gate located in the substrate and a second terminal located on the surface of the substrate, the second terminal being configured to be connected to a second-type memory cell, and a width of the second gate being less than a width of the first gate.
1. A semiconductor structure, comprising:
a substrate;
a first transistor comprising a first gate located in the substrate and a first terminal located on a surface of the substrate, the first terminal being configured to be connected to a first-type memory cell;
a second transistor comprising a second gate located in the substrate and a second terminal located on the surface of the substrate, the second terminal being configured to be connected to a second-type memory cell, and a width of the second gate being less than a width of the first gate;
a plurality of active regions arranged in an array in the substrate;
a shallow trench isolation structure located between the plurality of active regions; and,
wherein the plurality of active regions have at least one third active region; the third active region having the first transistor and the second transistor;
the first transistor and the second transistor being distributed on two opposite sides of an extension direction of the third active region, and the first transistor and the second transistor located in the third active region having a third common terminal.
2. The semiconductor structure according to claim 1 , further comprising a plurality of wordlines extending in a first direction;
a plurality of the third active regions being arranged in the array in the substrate, the plurality of the third active regions extending in a second direction, and the second direction is tilted by a preset angle relative to the first direction.
3. The semiconductor structure according to claim 2 , wherein in the second direction, ends of adjacent two of the third active regions close to each other are both the first transistor or the second transistor.
4. The semiconductor structure according to claim 3 , wherein one of the third active regions overlaps with adjacent two of the plurality of wordlines; and
the first transistor and the second transistor located in the one of the third active region regions correspond to the adjacent two of the plurality of wordlines respectively.
5. The semiconductor structure according to claim 4 , wherein the plurality of wordlines comprises first subwordlines and second subwordlines arranged alternately in a third direction, the third direction being perpendicular to the first direction;
the first transistor in the plurality of the third active regions arranged in the first direction overlap with the same first subwordline; and
the second transistor in the plurality of the third active regions arranged in the first direction overlap with the same second subwordline.
6. The semiconductor structure according to claim 5 , wherein a width of the second subwordlines is less than a width of the first subwordlines.
7. The semiconductor structure according to claim 6 , wherein the width of the second gate is ⅓ to ½ of the width of the first gate.
8. The semiconductor structure according to claim 2 , wherein in the first direction, in adjacent two of the plurality of the third active regions, the first transistor in one of the third active regions and the second transistor in the other one of the third active regions correspond to same one of the plurality of wordlines, and the one of the plurality of wordlines is periodically concave and convex.
9. The semiconductor structure according to claim 8 , wherein the width of the second gate is ½ to ⅔ of the width of the first gate.
10. A method of forming a semiconductor structure, comprising:
providing a substrate; and
forming a first transistor and a second transistor, the first transistor comprising a first gate located in the substrate and a first terminal located on a surface of the substrate, the first terminal being configured to be connected to a first-type memory cell, the second transistor comprising a second gate located in the substrate and a second terminal located on the surface of the substrate, the second terminal being configured to be connected to a second-type memory cell, and a width of the second gate being less than a width of the first gate;
forming an active region in the substrate;
forming a first gate groove and a second gate groove in the active region, a width of the second gate groove being less than a width of the first gate groove, the active region being divided by the first gate groove and the second gate groove into the first terminal, the second terminal and a common terminal between the first terminal and the second terminal; and
filling the first gate groove and the second gate groove with a gate material, to form the first gate and the second gate.
11. The method according to claim 10 , wherein the substrate further comprises a plurality of wordlines extending in a first direction; and
a plurality of the active regions are arranged in an array in the substrate, the active regions extend in a second direction, and the second direction is tilted by a preset angle relative to the first direction.
12. The method according to claim 11 , wherein in the second direction, ends of two adjacent the active regions close to each other are both the first transistor or the second transistor.
13. The method according to claim 12 , wherein one active region overlaps with adjacent two of the plurality of wordlines; and
the first transistor and the second transistor located in same one of the active regions correspond to the adjacent two of the plurality of wordlines respectively.
14. The method according to claim 13 , wherein the plurality of wordlines comprises first subwordlines and second subwordlines arranged alternately in a third direction, the third direction being perpendicular to the first direction;
the first transistor in the plurality of active regions arranged in the first direction overlap with same one of the first subwordlines; and
the second transistor in the plurality of active regions arranged in the first direction overlap with same one of the second subwordlines.
15. The method according to claim 11 , wherein in the first direction, in two adjacent the active regions, the first transistor in one of the two adjacent the active regions and the second transistor in the other one of the two adjacent the active regions correspond to same one of the plurality of wordlines, and the one of the plurality of wordlines is periodically concave and convex.