Display apparatus
A display apparatus includes an active area, an inactive area surrounding the active area, a pixel disposed in the active area, and a driver IC, a gate driver, a low-potential power supply line, a high-potential power supply line and a subframe controller disposed in the inactive area, wherein the subframe controller is disposed between the pixel and the gate driver.
1. A display apparatus, comprising:
a substrate;
a driver IC disposed on a side of the substrate; and
a gate driver disposed on a side of the substrate;
a pad for low-potential power disposed on a left side and a right side of the driver IC; and
a pad for high-potential power disposed on the left side and the right side of the driver IC,
wherein the gate driver includes:
a transistor T 1 including a gate electrode electrically connected to a node Q and a capacitor CQ, and electrically connected between an input terminal of a gate low voltage and an output node;
a transistor T 2 including a gate electrode electrically connected to a node QB and electrically connected between an input terminal of a gate high voltage and the output node;
a capacitor CB electrically connected between the input terminal of the gate high voltage and the gate electrode of the transistor T 2 ;
a transistor T 3 including a gate electrode electrically connected to an input terminal of a clock signal, and electrically connected between an input terminal of a start signal and the node Q;
a transistor T 4 electrically connected the input terminal of the gate high voltage;
a transistor T 5 electrically connected between the input terminal of the clock signal and the transistor T 2 ;
a transistor T 6 electrically connected between the input terminal of the gate high voltage and the transistor T 2 ; and
a transistor TA electrically connected between the transistor T 3 and the transistor T 1 .
2. The display apparatus according to claim 1 , further comprising:
a low potential power line disposed on the left side and the right side of the driver IC; and
a high potential power line disposed on the left side and the right side of the driver IC and a lower side of the driver IC.
3. The display apparatus according to claim 2 , wherein the high potential power line is disposed closer to the driver IC than the low potential power line on the left and right sides of the driver IC, respectively.
4. The display apparatus according to claim 1 , wherein the clock signal is applied to the gate electrode of the transistor T 2 , and
wherein the start signal is applied to the gate electrode of the transistor T 1 .
5. The display apparatus according to claim 1 , wherein the transistor T 4 is connected between the input terminal of the gate high voltage and the input terminal of the clock signal.
6. The display apparatus according to claim 1 , wherein the gate driver includes:
a Q 2 controller including the transistor T 3 and activating a node Q 2 in response to the clock signal;
a QB controller activating the node QB as opposed to the node Q 2 in response to the clock signal and including the transistor T 5 , the transistor T 4 , the transistor T 6 and the capacitor CB;
an output unit including the transistor T 1 serving as a pull-down element, the transistor T 2 serving as a pull-up element and the capacitor CQ; and
a stabilization unit including the transistor TA and blocking an electrical connection between the node Q 2 and the node Q when the node Q is bootstrapped.
7. The display apparatus according to claim 1 , wherein a first electrode of the transistor T 3 is connected to the input terminal of the start signal,
wherein a second electrode of the transistor T 3 is connected to a first electrode of the transistor TA, and
wherein a second electrode of the transistor TA is connected to the gate electrode of the transistor T 1 .
8. The display apparatus according to claim 1 , wherein the gate driver includes an oxide transistor.
9. The display apparatus according to claim 1 , further comprising: a pixel circuit including an oxide transistor on the substrate.
10. The display apparatus according to claim 1 , wherein the gate driver is driven at a scanning rate of less than 60 Hz.
11. The display apparatus according to claim 1 , further comprising:
a pixel disposed in an active area on the substrate; and
a subframe controller disposed on a side of the substrate,
wherein the subframe controller is disposed between the pixel and the gate driver,
wherein the driver IC includes a gate low voltage pad connected to the gate driver, and
wherein the gate low voltage pad is connected to a source electrode of the subframe controller.
12. The display apparatus according to claim 11 , wherein the driver IC includes:
a subframe control pad connected to a gate electrode of the subframe controller; and
a clock signal pad, a start signal pad and a gate high voltage pad connected to the gate driver.
13. The display apparatus according to claim 11 , wherein the driver IC includes a gate high voltage pad connected to the gate driver.
14. The display apparatus according to claim 11 , wherein a drain electrode of the subframe controller is electrically connected to an output terminal of the gate driver, and the output terminal of the gate driver is connected to the pixel.
15. The display apparatus according to claim 11 , wherein the subframe controller is in a turn-off state during a main frame period of the pixel and is in a turn-on state during a subframe period of the pixel.
16. The display apparatus according to claim 15 , wherein a drain electrode of the subframe controller outputs an output voltage of −9 V when the subframe controller is in the turn-on state.
17. The display apparatus according to claim 11 , wherein a drain electrode of the subframe controller is connected to a line extended from the gate driver to the pixel.