Semiconductor device with gate dielectric formed using selective deposition
A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.
1. A semiconductor device, comprising:
a plurality of semiconductor layers arranged one above another;
source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers;
a gate structure surrounding each of the plurality of semiconductor layers, the gate structure comprising interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer; and
gate spacers spacing apart the gate structure from the source/drain epitaxial regions, wherein a top position of the high-k dielectric layer is lower than top positions of the gate spacers, and the high-k dielectric layer is spaced apart from one of the gate spacers by a void region.
2. The semiconductor device of claim 1 , wherein the top position of the high-k dielectric layer is lower than a top position of the gate metal.
3. The semiconductor device of claim 1 , wherein end surfaces of the high-k dielectric layer are respectively aligned with end surfaces of the interfacial layers.
4. The semiconductor device of claim 1 , further comprising:
a self-assembled-monolayer below a topmost one of the plurality of semiconductor layers.
5. The semiconductor device of claim 4 , wherein the self-assembled-monolayer is in contact with a sidewall of the gate structure.
6. The semiconductor device of claim 1 , wherein the high-k dielectric layer continuously extends from a bottommost one of the plurality of semiconductor layers to a topmost one of the plurality of semiconductor layers.
7. The semiconductor device of claim 1 , wherein the gate structure comprises a plurality of the high-k dielectric layers respectively over the plurality of semiconductor layers, and the high-k dielectric layers are spaced apart from each other.
8. The semiconductor device of claim 1 , wherein the gate metal is in contact with the gate spacers.
9. A semiconductor device, comprising:
source/drain epitaxial structures over a substrate;
a plurality of channel layers extending between the source/drain epitaxial structures;
a gate structure wrapping around the plurality of channel layers, the gate structure comprising a high-k dielectric layer and a gate metal over the high-k dielectric layer;
a first gate spacer between the gate structure and a first one of the source/drain epitaxial structures; and
a second gate spacer between the gate structure and a second one of the source/drain epitaxial structures,
wherein the high-k dielectric layer is spaced apart from the first gate spacer.
10. The semiconductor device of claim 9 , wherein the gate metal interposes the high-k dielectric layer and the first gate spacer.
11. The semiconductor device of claim 9 , wherein the high-k dielectric layer is spaced apart from the second gate spacer.
12. The semiconductor device of claim 11 , wherein the gate metal interposes the high-k dielectric layer and the second gate spacer.
13. The semiconductor device of claim 9 , wherein the high-k dielectric layer is spaced apart from the first gate spacer by a void.
14. The semiconductor device of claim 9 , wherein the gate metal is in contact with end surfaces of the high-k dielectric layer.
15. A semiconductor device, comprising:
a source region and a drain region spaced apart in a first direction over a substrate;
a plurality of channel regions extending between the source region and the drain region;
a high-k dielectric layer over the plurality of channel regions, wherein in a cross section taken along a second direction perpendicular to the first direction, the high-k dielectric layer continuously extending from below a bottommost one of the channel regions to above a topmost one of the channel regions;
a gate metal over the high-k dielectric layer, wherein in a cross section taken along the first direction, the gate metal has a top surface higher than a top surface of the high-k dielectric layer; and
gate spacers interfacing opposite sidewalls of the gate metal, wherein the gate spacers are separated from the high-k dielectric layer by void regions.
16. The semiconductor device of claim 15 , wherein the gate spacers are separated from the high-k dielectric layer at least further by the gate metal.
17. The semiconductor device of claim 15 , wherein in the cross section taken along the first direction, the gate metal wraps around three sides of the high-k dielectric layer.
18. The semiconductor device of claim 15 , wherein in the cross section taken along the first direction, the high-k dielectric layer resembles a linear pattern.
19. The semiconductor device of claim 15 , further comprising:
a self-assembled-monolayer in contact with the plurality of channel regions.
20. The semiconductor device of claim 19 , wherein the top surface of the high-k dielectric layer is higher than a top surface of the self-assembled-monolayer.