IP Library › Granted Patent US 12,230,498
Granted Patent B2
US 12,230,498 · App. 17/222,195 · Granted Feb 18, 2025

Method for manufacturing semiconductor device including air gap

Inventors: Dain Lee (Hwaseong-si, KR); Yoongoo Kang (Hwaseong-si, KR); Wonseok Yoo (Seoul, KR); Jinwon Ma (Hwaseong-si, KR); Kyungwook Park (Pohang-si, KR); Changwoo Seo (Suwon-si, KR); Suyoun Song (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/0228C23C16/45525H01L21/02362C23C16/345C23C16/36
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Quick Facts
Patent No.
US 12,230,498
App. No.
17/222,195
Granted
Feb 18, 2025
Kind
B2
Abstract

A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

Claims (44)

1. A method for manufacturing a semiconductor device, comprising:

loading a semiconductor substrate including a silicon oxide film into a chamber;

depositing a seed layer on the silicon oxide film by supplying a first silicon source material;

supplying a purge gas;

depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material and subsequently supplying a silicon source material having a material composition identical to the first silicon source material;

depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material; and

forming an air gap by using a cleaning process, the cleaning process including removing portions of the silicon oxide film and of the seed layer.

2. The method according to claim 1 , wherein the base source material comprises at least one of a carbon source material or a boron source material.

3. The method according to claim 1 , wherein the depositing the protective layer further comprises supplying the nitrogen source material after supplying the base source material and before supply of the silicon source material having the material composition identical to the first silicon source material.

4. The method according to claim 1 , wherein the seed layer has a thickness of 20 Å or less.

5. The method according to claim 1 , wherein the protective layer has a thickness of 20 Å or less.

6. The method according to claim 1 , wherein each of the first silicon source material and the second silicon source material include a halogen-substituted silane-based silicon precursor.

7. The method according to claim 1 , wherein the purge gas includes hydrogen.

8. A method for manufacturing a semiconductor device, comprising:

forming a first impurity region on a substrate and a second impurity region on the substrate;

recessing the first impurity region to form a contact recess;

forming a bit line structure extending in the contact recess in one direction, the bit line structure contacting the first impurity region, and the bit line structure having a first side wall and a second side wall;

forming an inner spacer on the first side wall and the second side wall of the bit line structure;

forming a recess filler in a remaining region of the contact recess;

forming a sacrificial spacer on the inner spacer and on the recess filler;

forming an outer spacer on the sacrificial spacer;

forming a storage node contact contacting the second impurity region, the contacting the second impurity region performed at an outside of the outer spacer;

partially removing the sacrificial spacer and remaining portion of the outer spacer, to form an air gap between the outer spacer and the inner spacer;

forming a landing pad on the storage node contact;

forming a trench defining the landing pad, the forming the trench exposing an upper surface of the remaining portion of sacrificial spacer; and

forming a pad isolation insulating layer filling the trench,

wherein the forming the outer spacer is performed in a chamber without breaking vacuum and comprises

depositing a seed layer using a first silicon source material,

supplying a purge gas,

depositing a protective layer on the seed layer by repeating a first cycle comprising supplying a carbon source material and supplying the silicon source material having the material composition identical to the first silicon source material, and

depositing a preliminary main spacer on the protective layer by repeating a second cycle comprising supplying a second silicon source material and supplying a first nitrogen source material.

9. The method according to claim 8 , wherein,

the forming the outer spacer comprises anisotropically etching the seed layer, the protective layer and the preliminary main spacer, to form a seed spacer, a protective spacer and a main spacer, and

the forming the air gap comprises partially removing the seed spacer.

10. The method according to claim 8 , wherein the depositing the protective layer further comprises:

supplying a second nitrogen source material after supply of the carbon source material and before supply of the first silicon source material.

11. The method according to claim 8 , wherein the seed layer is a silicon thin film not comprising carbon and not comprising nitrogen.

12. The method according to claim 11 , wherein the forming the air gap comprises removing portions of the sacrificial spacer and the outer spacer through a cleaning process.

13. The method of claim 1 , wherein the base source material comprises a carbon source material.

14. The method of claim 1 , wherein the base source material comprises a boron source material.

15. The method of claim 10 , wherein the protective layer has a thickness of 20 Å or less.

16. The method of claim 6 , wherein the purge gas includes hydrogen.

17. The method of claim 1 , wherein the chamber is a plasma-enhanced atomic layer deposition (PEALD) chamber.

18. The method of claim 8 , wherein the chamber is a plasma-enhanced atomic layer deposition (PEALD) chamber.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2021
From: LEE, DAIN; KANG, YOONGOO; YOO, WONSEOK; MA, JINWON; PARK, KYUNGWOOK; SEO, CHANGWOO; SONG, SUYOUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 055836/0244 →
Priority Claims (1)
KR 10-2020-0122830 · Sep 23, 2020 · national
Continuity (1)
Related Publication 20220093387A1 · Mar 24, 2022
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