Integrated circuit layout and method thereof
View Patent ↗An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.
1. A method, comprising:
forming a first active region and a second active region over a substrate and extending along a first direction, wherein the first active region and the second active region are separated by an isolation structure;
forming a first gate structure over the first active region;
forming a plurality of second gate structures over the second active region, the plurality of second gate structures being arranged along the first direction and separated from each other, and wherein along the first direction, a sum of gate lengths of the second gate structures is n times a gate length of the first gate structure, and n is a positive integer and is greater than 1, and wherein each of the gate lengths of the second gate structures is the same as the gate length of the first gate structure, wherein the plurality of second gate structures collectively serve as a gate of a same transistor, wherein the second active region has a portion between the second gate structures, and the portion of the second active region between the second gate structures is free of a source/drain region;
forming first source/drain regions in the first active region; and
forming second source/drain regions in the second active region, wherein portions of the second active region between two adjacent second gate structures have lower dopant concentrations than the second source/drain regions.
2. The method of claim 1 , further comprising forming gate spacers on opposite sidewalls of the second gate structures.
3. The method of claim 1 , wherein a portion of the second active region laterally between at least two of the second gate structures are un-doped.
4. The method of claim 1 , wherein from a top view, the second active region is a continuous active region overlapped by the second gate structures.
5. A method for forming an integrated circuit (IC) structure, comprising:
forming a first active region and a second active region over a substrate;
forming a first gate over the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region; and
forming a second gate over the second active region and comprising a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1, and wherein a first set of the gate structures of the second gate have a first gate length, the first gate length is m times the first effective gate length, a second set of the gate structures have a second gate length, the second gate length is o times the first effective gate length, wherein m and o are different positive integers, wherein the first set of the gate structures and the second set of the gate structures are of a single transistor.
6. The method of claim 5 , wherein the gate structures of the second gate are electrically connected to a same voltage node.
7. The method of claim 5 , further comprises forming gate spacers on opposite sidewalls of each of the gate structures of the second gate.
8. The method of claim 5 , further comprises forming source/drain regions in the second active region, the source/drain regions are respectively adjacent to outmost two of the gate structures of the second gate, and portions of the second active region between outermost two of the gate structures of the second gate has a dopant concentration lower than a dopant concentration of the source/drain regions.
9. The method of claim 5 , wherein along the first direction, the first set of the gate structures are not between adjacent two of the second set of the gate structures.
10. The method of claim 5 , wherein the first effective gate length is a minimum gate length in the IC structure.
11. The method of claim 5 , wherein the first active region comprises one or more semiconductor fins.
12. The method of claim 5 , wherein the second active region comprises one or more semiconductor fins.
13. The method of claim 5 , wherein there is no source/drain region between any adjacent two of the gate structures of the second gate.
14. A method for forming an integrated circuit (IC) structure, comprising:
forming a first transistor, comprising:
forming a first active region and a second active region over a substrate, wherein the first and second active regions extend along a first direction;
forming an isolation structure over the substrate and separating the first active region from the second active region;
forming a gate having gate structures disposed on the first and second active regions, respectively, wherein along the first direction, an effective gate length of the gate is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and is greater than 1, wherein the gate structures are separated from each other and are electrically connected to a same voltage node, wherein the gate structures are of the same first transistor, wherein there is no source/drain region in a portion of the first active region between adjacent two of the gate structures;
forming gate spacers on sidewalls of each of the gate structures of the gate;
forming a first source/drain region in the first active region; and
forming a second source/drain region in the second active region; and
forming a second transistor having a gate length substantially equal to the critical dimension of the technology node of the first transistor.
15. The method of claim 14 , wherein the gate structures of the first transistor have substantially a same gate length equal to the critical dimension of the technology node of the first transistor.
16. The method of claim 14 , wherein at least two of the gate structures of the first transistor have different threshold voltages.
17. The method of claim 14 , wherein a first set of the gate structures has a first gate length, the first gate length is m times the critical dimension of the technology node of the first transistor, a second set of the gate structures has a second gate length, and the second gate length is o times the critical dimension of the technology node of the first transistor, wherein m and o are different positive integers.
18. The method of claim 17 , wherein a number of the first set of the gate structures is different from a number of the second set of the gate structures.
19. The method of claim 14 , further comprising:
forming a first contact over the first active region, wherein the first contact is at a first side of the first active region, and the first source/drain region is at a second side of the first active region opposite to the first side of the first active region;
forming a second contact over the second active region, wherein the second contact is at a first side of the second active region, and the second source/drain region is at a second side of the second active region opposite to the first side of the second active region; and
forming a metal line electrically connecting the first contact and the second contact.
20. The method of claim 14 , wherein from a top view, the first active region is a continuous active region overlapped by the adjacent two of the gate structures.