Method of reading data from self-selecting memory, self-selecting memory performing the same and method of operating self-selecting memory using the same
A method of reading data from a self-selecting memory includes generating a read pulse that has a polarity opposite to that of a write pulse. The write pulse writes data into a target memory cell in the self-selecting memory. The read pulse is applied to the target memory cell. The read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse. A slope of the second edge of the read pulse is adjusted such that an undershoot or overshoot on the second edge of the read pulse increases.
1. A method of reading data from a self-selecting memory, the method comprising:
generating a read pulse that has a polarity opposite to that of a write pulse, wherein the write pulse writes data into a target memory cell in the self-selecting memory, wherein the read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse;
adjusting a slope of the second edge of the read pulse wherein an undershoot or overshoot of the second edge of the read pulse increases; and
applying the read pulse to the target memory cell.
2. The method of claim 1 , wherein, when the write pulse has a negative polarity, the read pulse has a positive polarity, and the second edge of the read pulse is a falling edge.
3. The method of claim 2 , further comprising increasing an undershoot on the falling edge of the read pulse by decreasing a falling time of the falling edge of the read pulse.
4. The method of claim 3 , further comprising shortening the falling time of the falling edge of the read pulse as a distance between a write/read circuit that generates the read pulse and the target memory cell increases.
5. The method of claim 1 , wherein, when the write pulse has a positive polarity, the read pulse has a negative polarity, and the second edge of the read pulse is a rising edge.
6. The method of claim 5 , further comprising increasing an overshoot on the rising edge of the read pulse by decreasing a rising time of the rising edge of the read pulse.
7. The method of claim 6 , further comprising shortening the rising time of the rising edge of the read pulse as a distance between a write/read circuit that generates the read pulse and the target memory cell increases.
8. The method of claim 1 , further comprising decreasing an overshoot or undershoot on the first edge of the read pulse by adjusting a slope of the first edge of the read pulse.
9. The method of claim 8 , wherein, when the write pulse has a negative polarity, the read pulse has a positive polarity, and the first edge of the read pulse is a rising edge.
10. The method of claim 9 , further comprising decreasing overshoot on the rising edge of the read pulse by increasing a rising time of the rising edge of the read pulse.
11. The method of claim 8 , wherein, when the write pulse has a positive polarity, the read pulse has a negative polarity, and the first edge of the read pulse is a falling edge.
12. The method of claim 11 , further comprising decreasing an undershoot on the falling edge of the read pulse by increasing a falling time of the falling edge of the read pulse.
13. The method of claim 1 , wherein the read pulse is fixed to one of a positive polarity or a negative polarity.
14. The method of claim 13 , wherein the write pulse has both the positive polarity and the negative polarity.
15. The method of claim 1 , wherein the target memory cell includes:
a first electrode connected to a bitline;
a second electrode connected to a wordline; and
a self-selecting material disposed between the first electrode and the second electrode.
16. The method of claim 15 , wherein the self-selecting material includes a chalcogenide material.
17. The method of claim 15 , wherein the target memory cell does not include a switching element.
18. A self-selecting memory, comprising:
a self-selecting memory cell array that includes a plurality of self-selecting memory cells; and
a write/read circuit that controls a data write operation and a data read operation on the self-selecting memory cell array,
wherein, in the data read operation on a target memory cell in the self-selecting memory cell array, the write/read circuit generates a read pulse that has a polarity opposite to that of a write pulse and applies the read pulse to the target memory cell, wherein the write pulse writes data into the target memory cell,
wherein the read pulse has a first edge that is a starting point of the read pulse and a second edge that is an ending point of the read pulse, and
wherein a slope of the second edge of the read pulse is adjusted wherein an undershoot or overshoot on the second edge of the read pulse increases.
19. The self-selecting memory of claim 18 , wherein the write/read circuit includes:
a write driver that generates the write pulse;
a read driver that generates the read pulse; and
an edge controller that adjusts the slope of the second edge of the read pulse.
20. A method of operating a self-selecting memory, the method comprising:
performing a data write operation on a target memory cell in the self-selecting memory by using a write pulse that has a first polarity; and
performing a data read operation on the target memory cell by using a read pulse that has a second polarity opposite to the first polarity,
wherein performing the data read operation includes:
generating the read pulse; and
applying the read pulse to the target memory cell,
wherein generating the read pulse includes:
adjusting a slope of a first edge of the read pulse by increasing a transition time of the first edge of the read pulse wherein an overshoot or undershoot of the first edge decreases, wherein the first edge is a starting point of the read pulse;
adjusting a slope of a second edge of the read pulse by decreasing a transition time of the second edge of the read pulse wherein an undershoot or overshoot of the second edge increases, wherein the second edge is an ending point of the read pulse; and
adjusting the slope of the second edge of the read pulse such that the transition time of the second edge of the read pulse becomes shorter as a distance between a write/read circuit that generates the read pulse and the target memory cell increases, and
wherein, in response to adjusting the slopes of the first and second edges of the read pulse, the transition times of the first and second edges of the read pulse become different from each other.