Semiconductor package
A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.
1. A semiconductor package, comprising:
a redistribution substrate that has a first surface and a second surface that face each other;
a semiconductor chip disposed on the first surface of the redistribution substrate; and
a plurality of solder patterns disposed on the second surface of the redistribution substrate,
wherein the redistribution substrate includes:
a first under-bump pattern; and
a plurality of second under-bump patterns that are laterally spaced apart from the first under-bump pattern,
wherein each of the first under-bump and the plurality of second under-bump patterns includes:
a first part coupled to one of the plurality of solder patterns; and
a second part formed on the first part and that is wider than the first part,
wherein the first part of the first under-bump pattern includes a plurality of first parts,
wherein the second part of the first under-bump pattern is connected to the plurality of the first parts of the first under-bump pattern,
wherein the redistribution substrate further includes an under-bump seed pattern that covers a sidewall of the first part and a bottom surface of the second part of the first under-bump and the plurality of second under-bump patterns, and
a dielectric layer that exposes a lowermost surface of the under-bump seed pattern.
2. The semiconductor package as claimed in claim 1 , wherein the lowermost surface of the under-bump seed pattern is located at a higher level than a bottom surface of the first under-bump and the plurality of second under-bump patterns.
3. The semiconductor package as claimed in claim 1 , wherein the under-bump seed pattern covers a portion of the sidewall of first part of the first under-bump and the plurality of second under-bump patterns and exposes another portion of the sidewall the first part of first under-bump and the plurality of second under-bump patterns.
4. The semiconductor package as claimed in claim 1 , wherein a bottom surface of the first under-bump pattern and the plurality of second under-bump patterns is located at a higher level than the second surface of the redistribution substrate.
5. The semiconductor package as claimed in claim 1 , wherein the lowermost surface of the under-bump seed pattern is located at a higher level than the second surface of the redistribution substrate.
6. The semiconductor package as claimed in claim 1 ,
wherein the redistribution substrate further includes a first conductive pattern disposed on a top surface of the first under-bump pattern and that is electrically connected to the first under-bump pattern,
wherein the first under-bump pattern is thicker than the first conductive pattern.
7. The semiconductor package as claimed in claim 1 , wherein a thickness of the first under-bump pattern is in a range from about 5 μm to about 20 μm.
8. The semiconductor package as claimed in claim 1 , wherein the second part of the first under-bump pattern is wider than the second part of the plurality of second under-bump patterns.
9. The semiconductor package as claimed in claim 1 , wherein each of the plurality of second under-bump patterns includes one first part and one second part.
10. A semiconductor package, comprising:
a redistribution substrate; and
a semiconductor chip disposed on the redistribution substrate,
wherein the redistribution substrate includes:
a first under-bump pattern; and
a plurality of second under-bump patterns that are laterally spaced apart from the first under-bump pattern,
wherein each of the first under-bump pattern and the plurality of second under-bump patterns includes:
a first part; and
a second part formed on the first part and that is wider than the first part,
wherein the first part of the first under-bump pattern includes a plurality of first parts,
wherein the second part of the first under-bump pattern in connected to the plurality of the first parts of the first under-bump pattern,
wherein the second part of the first under-bump pattern is wider than the second part of the plurality of second under-bump patterns,
wherein the redistribution substrate further includes an under-bump seed pattern that covers a sidewall of the first part and a bottom surface of the second part of the first under-bump and the plurality of second under-bump patterns, and
wherein a bottom surface of the first under-bump pattern and the plurality of second under-bump patterns is located at a higher level than a bottom surface of the redistribution substrate.
11. The semiconductor package as claimed in claim 10 , wherein the redistribution substrate includes a dielectric layer that does not contact a lowermost surface of the under-bump seed pattern.
12. The semiconductor package as claimed in claim 10 , wherein a lowermost surface of the under-bump seed pattern is located at a same or higher level than a bottom surface of the first under-bump and the plurality of second under-bump patterns.
13. The semiconductor package as claimed in claim 10 , wherein a lowermost surface of the under-bump seed pattern is located at a higher level than the bottom surface of the redistribution substrate.
14. The semiconductor package as claimed in claim 10 , wherein the under-bump seed pattern covers a portion of the sidewall of the first part of the first under-bump and the plurality of second under-bump patterns and exposes another portion of the sidewall of the first part of first under-bump and the plurality of second under-bump patterns.
15. The semiconductor package as claimed in claim 10 ,
wherein the redistribution substrate further includes a first conductive pattern disposed on a top surface of the first under-bump pattern and that is electrically connected to the first under-bump pattern,
wherein the first under-bump pattern is thicker than the first conductive pattern.
16. The semiconductor package as claimed in claim 10 ,
wherein the under-bump seed pattern has a first thickness on a bottom surface of the second part of the first under-bump pattern, and
a level difference between a lowermost surface of the under-bump seed pattern and the bottom surface of the redistribution substrate ranges from about 1 to about 10 times the first thickness.
17. A semiconductor package, comprising:
a redistribution substrate; and
a semiconductor chip disposed on the redistribution substrate,
wherein the redistribution substrate includes:
a first under-bump pattern;
a first conductive pattern disposed on a top surface of the first under-bump pattern and that is electrically connected to the first under-bump pattern; and
a plurality of second under-bump patterns that are laterally spaced apart from the first under-bump pattern,
wherein each of the first under-bump pattern and the plurality of second under-bump patterns includes:
a first part; and
a second part formed on the first part and that is wider than the first part,
wherein the first part of the first under-bump pattern includes a plurality of first parts,
wherein the second part of the first under-bump pattern is connected to the plurality of the first parts of the first under-bump pattern,
wherein the first under-bump pattern is thicker than the first conductive pattern.
18. The semiconductor package as claimed in claim 17 , wherein the redistribution substrate includes an under-bump seed pattern that covers a sidewall of the first part and a bottom surface of the second part of the first under-bump pattern and the plurality of second under-bump patterns and a dielectric layer that exposes a lowermost surface of the under-bump seed pattern.
19. The semiconductor package as claimed in claim 17 , wherein a bottom surface of the first under-bump pattern and the plurality of second under-bump patterns is located at a higher level than a bottom surface of the redistribution substrate.
20. The semiconductor package as claimed in claim 17 ,
wherein the redistribution substrate further includes an under-bump seed pattern that covers a side wall of the first part and a bottom surface of the second part of the first under-bump and the plurality of second under-bump patterns, and
wherein the under-bump seed pattern covers a portion of the sidewall of first part of the first under-bump and the plurality of second under-bump patterns and exposes another portion of the sidewall the first part of first under-bump and the plurality of second under-bump patterns.