Vertical gallium oxide (GA2O3) power FETs
A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga 2 O 3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga 2 O 3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.
1. A vertical gallium oxide (Ga2O3) device comprising: a
substrate;
an n-type Ga2O3 drift layer disposed on a surface of the substrate;
an n-type semiconducting channel extending from a surface of the n-type Ga2O3 drift layer, the n-type semiconducting channel being one of fin-shaped or nanowire shaped; an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the n-type semiconducting channel; no p-type semiconducting layer being used in the vertical gallium oxide (Ga2O3) device;
a first dielectric layer directly on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel;
a conductive gate layer deposited on at least a portion of the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer;
a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls; and
an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer; and
a resistive terminal component extending from a first lateral surface of the n-type Ga2O3 drift layer to a second lateral surface of the n-type Ga2O3 drift layer and from said surface of the n-type Ga2O3 drift layer and another surface of the n-type Ga2O3 drift layer, said another surface located between said surface of the n-type Ga2O3 drift layer and said surface of the substrate.
2. The vertical gallium oxide (Ga2O3) device of claim 1 wherein the conductive gate layer is deposited on a portion of the first dielectric layer; the vertical gallium oxide (Ga2O3) device also comprising a third dielectric layer disposed over a portion of the first dielectric layer that is not covered by the conductive gate layer; said first and second lateral surfaces of the n-type Ga2O3 drift layer extending from said surface of the n-type Ga2O3 drift layer to said surface of the substrate.
3. The vertical gallium oxide (Ga2O3) device of claim 2 wherein the second dielectric layer also covers the conductive gate layer over the n-type Ga2O3 drift layer and a portion of the first dielectric layer, the portion of the first dielectric layer not being covered by the conductive gate layer; said second dielectric layer being in contact with said third dielectric layer.
4. The vertical gallium oxide (Ga2O3) device of claim 3 further comprising:
a field plate conductive layer disposed on the third dielectric layer, said second dielectric layer being in contact with the field plate conductive layer; and
a fourth dielectric disposed on a part of the portion of the second dielectric layer and extending from a portion of a sidewall of the second dielectric layer to the field plate conductive layer and between the second dielectric layer and the ohmic source contact.
5. The vertical gallium oxide (Ga2O3) device of claim 4 wherein the ohmic source contact is disposed over a portion of the second dielectric layer extending from the conductive gate layer to the n-type source layer, over the fourth dielectric, and extends from the fourth dielectric to a portion of the field plate conductive layer; the portion of the field plate conductive layer being in contact with the ohmic source contact.
6. A vertical group III trioxide transistor comprising:
a substrate;
an n-type group III trioxide material drift layer on a surface of the substrate, the n-type group III trioxide material comprising one of Ga 2 O 3 , In 2 O 3 , (Al x Ga 1-x ) 2 O 3 or (Al x In 1-x ) 2 O 3 or a combination thereof;
an n-type semiconducting channel extending from a surface of the n-type group III trioxide material drift layer; an n-type source layer disposed on the n-type semiconducting channel; the n-type source layer has a higher doping concentration than the n-type semiconducting channel;
the n-type group III trioxide material drift layer, the n-type semiconducting channel and the source layer being n-type group III trioxide semiconducting material layers;
no p-type semiconducting layer being used in the vertical group III trioxide transistor;
a first dielectric layer deposited directly on the n-type group III trioxide material drift layer and on sidewalls of the n-type semiconducting channel;
a conductive gate layer on the first dielectric layer including a portion on the sidewall but not connected to the n-type source layer;
a second dielectric layer deposited over a sidewall of the n-type source layer, the sidewall of the n-type semiconducting channel, the conductive gate layer and the gate dielectric layer;
a source-connected metal layer deposited over the n-type source layer and the second dielectric layer; and
a resistive terminal component extending from a first lateral surface of the n-type group III trioxide material drift layer to a second lateral surface of the n-type group III trioxide material drift layer and from said surface of the n-type group III trioxide material drift layer and another surface of n-type group III trioxide material drift layer, said another surface located between said surface of the n-type group III trioxide material drift layer and said surface of the substrate;
said first and second lateral surfaces of the n-type group III trioxide material drift layer extending from said surface of the n-type group III trioxide material drift layer to said surface of the substrate.
7. The vertical group III trioxide transistor of claim 6 wherein the conductive gate layer is deposited on a portion of the first dielectric layer; the vertical group III trioxide transistor also comprising a third dielectric layer disposed over a portion of the first dielectric layer that is not covered by the conductive gate layer.
8. The vertical group III trioxide transistor of claim 7 wherein the second dielectric layer also covers the conductive gate layer over the n-type group III trioxide material drift layer and a portion of the first dielectric layer, the portion of the first dielectric layer not being covered by the conductive gate layer; said second dielectric layer being in contact with said third dielectric layer.
9. The vertical group III trioxide transistor of claim 8 further comprising:
an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the ohmic source contact being configured not to be in electrical contact with the conductive gate layer.
10. The vertical group III trioxide transistor of claim 9 further comprising:
a field plate conductive layer disposed on the third dielectric layer, said second dielectric layer being in contact with the field plate conductive layer; and
a fourth dielectric disposed on a part of the portion of the second dielectric layer and extending from a portion of a sidewall of the second dielectric layer to the field plate conductive layer and between the second dielectric layer and the ohmic source contact.
11. The vertical group III trioxide transistor of claim 10 wherein the ohmic source contact is disposed over a portion of the second dielectric layer extending from the conductive gate layer to the n-type source layer, over the fourth dielectric, and extends from the fourth dielectric to a portion of the field plate conductive layer, the portion of the field plate conductive layer being in contact with the ohmic source contact.