Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices
Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.
1. A method of forming a semiconductor device, the method comprising:
forming a ferroelectric dielectric layer over a substrate, forming the ferroelectric dielectric layer comprising:
forming an alternating sequence of dielectric layers, forming the alternating sequence of dielectric layers comprising:
depositing a first dielectric layer over the substrate, wherein at least a part of the first dielectric layer is amorphous; and
forming a plurality of pairs of dielectric layers over the first dielectric layer, forming each pair of layers comprising:
depositing a dopant-source layer comprising dopants; and
depositing a second high-k dielectric layer over the dopant-source layer, wherein at least a part of the second high-k dielectric layer is amorphous; and
after forming the alternating sequence of dielectric layers, performing a first anneal to transform the alternating sequence of dielectric layers to the ferroelectric dielectric layer, wherein an upper surface of an uppermost layer of the second high-k dielectric layer is exposed during the first anneal.
2. The method of claim 1 , wherein the substrate comprises a semiconductor substrate and an interfacial layer over the semiconductor substrate.
3. The method of claim 2 , further comprising forming a gate electrode directly over the ferroelectric dielectric layer.
4. The method of claim 3 , wherein the interfacial layer and the ferroelectric dielectric layer form a dielectric stack, wherein a capacitance of the dielectric stack is negative for at least some range of gate bias.
5. The method of claim 1 , wherein a dopant profile of the dopants in the ferroelectric dielectric layer has at least two distinct convex regions.
6. The method of claim 5 , wherein after performing the first anneal a maximum peak of the dopant profile of the dopants in the ferroelectric dielectric layer is offset from a lower surface of the ferroelectric dielectric layer.
7. The method of claim 1 , wherein the dopant-source layer has a thickness in a range between 0.5 Å and 20 Å.
8. The method of claim 7 , wherein the dopant-source layer comprises Si, La, or Zr atoms.
9. A method of forming a semiconductor device, the method comprising:
forming one or more dielectric layers over a substrate, the one or more dielectric layers having a recess;
forming a first hafnium oxide layer in the recess;
depositing a first dopant-source layer over the first hafnium oxide layer;
forming a second hafnium oxide layer over the first dopant-source layer;
depositing a second dopant-source layer over the second hafnium oxide layer;
forming a third hafnium oxide layer over the second dopant-source layer; and
performing a first anneal to transform the first hafnium oxide layer, the first dopant-source layer, the second hafnium oxide layer, the second dopant-source layer, and the third hafnium oxide layer to a ferroelectric dielectric layer, wherein the first anneal is performed while an upper surface of the third hafnium oxide layer is exposed, the ferroelectric dielectric layer being an orthorhombic-phase polycrystalline hafnium oxide dielectric layer.
10. The method of claim 9 , wherein depositing the first hafnium oxide layer, the second hafnium oxide layer, and the third hafnium oxide layer comprises performing an atomic layer deposition process.
11. The method of claim 10 , further comprising forming a conductive element over the ferroelectric dielectric layer.
12. The method of claim 9 , wherein a thickness of the third hafnium oxide layer and a thickness of the first hafnium oxide layer is less than a thickness of the second hafnium oxide layer.
13. The method of claim 9 , wherein a thickness of the third hafnium oxide layer and a thickness of the first hafnium oxide layer is greater than a thickness of the second hafnium oxide layer.
14. The method of claim 9 , further comprising forming one or more additional hafnium oxide layers and forming one or more additional dopant-source layers, wherein adjacent hafnium oxide layers are separated by a dopant-source layer of the one or more additional dopant-source layers.
15. A method of forming a semiconductor device, the method comprising:
forming a ferroelectric dielectric layer over a substrate, wherein the ferroelectric dielectric layer is an orthorhombic-phase polycrystalline doped hafnium oxide, wherein dopants in the ferroelectric dielectric layer are distributed non-uniformly within the ferroelectric dielectric layer, wherein forming the ferroelectric dielectric layer comprises:
forming alternating layers of a high-k dielectric material layer and a dopant-source material layer, and
annealing to transform the alternating layers of the high-k dielectric material layer and the dopant-source material layer, wherein an uppermost layer of the high-k dielectric material layer is exposed during the annealing; and
forming a conductive element over the ferroelectric dielectric layer.
16. The method of claim 15 , wherein the ferroelectric dielectric layer has a thickness between 1 nm and 10 nm.
17. The method of claim 15 , wherein the conductive element comprises a transistor gate electrode.
18. The method of claim 15 , wherein a dopant profile of the dopants in the ferroelectric dielectric layer has at least two peaks.
19. The method of claim 15 , wherein a peak of a dopant profile of the dopants is offset from a lower surface and an upper surface of the ferroelectric dielectric layer.
20. The method of claim 15 , wherein the high-k dielectric material layers have different thicknesses.