IP Library › Granted Patent US 12,249,578
Granted Patent B2
US 12,249,578 · App. 17/356,199 · Granted Mar 11, 2025

Semiconductor package structure and method for manufacturing the same

Inventor: Hsu-Nan Fang (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L23/535H01L24/32H01L25/16H01L24/73H01L24/83H01L2224/32145H01L2224/73253H01L2224/83896H01L2924/19015H01L2924/19041
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Quick Facts
Patent No.
US 12,249,578
App. No.
17/356,199
Granted
Mar 11, 2025
Kind
B2
Abstract

A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes an electronic component having a first surface, a second surface opposite to the first surface and a circuit structure closer to the first surface than to the second surface. The semiconductor package structure also includes a passive component connected to the second surface of the electronic component. The semiconductor package structure further includes a conductive element extending into the electronic component and configured to electrically connect the circuit structure with the passive component.

Claims (20)

1. A semiconductor package structure, comprising:

an electronic component having a first surface, a second surface opposite to the first surface and a circuit structure closer to the first surface than to the second surface, wherein the electronic component is a semiconductor die comprising a transistor;

a passive component connected to the second surface of the electronic component; and

a conductive element extending into the electronic component and configured to electrically connect the circuit structure with the passive component,

wherein the passive component comprises a conductive structure, and the conductive element is disposed within the passive component and electrically connected to the conductive structure, and wherein the conductive element has a first portion within the electronic component, and the first portion is tapered toward the first surface of the electronic component,

and wherein the conductive element has a second portion within the passive component, and a sidewall of the first portion is substantially aligned with a sidewall of the second portion in a cross-sectional view,

and wherein the electronic component comprises a conductive via electrically connected to the conductive element, and an interface between the conductive via and the first portion of the conductive element is closer to the second surface of the electronic component than to the first surface of the electronic component.

2. The semiconductor package structure of claim 1 , wherein a portion of a top surface of the conductive via is exposed by the conductive element.

3. The semiconductor package structure of claim 1 , further comprising:

a dielectric structure disposed between the passive component and the electronic component,

wherein the conductive element penetrates the dielectric structure.

4. The semiconductor package structure of claim 3 , wherein the dielectric structure comprises silicon oxide.

5. A semiconductor package structure, comprising:

an electronic component having a first surface, a second surface opposite to the first surface and a circuit structure closer to the first surface than to the second surface, wherein the electronic component is a semiconductor die comprising a transistor;

a passive component connected to the second surface of the electronic component; and

a conductive element extending into the electronic component and configured to electrically connect the circuit structure with the passive component,

wherein the passive component comprises a conductive structure, and the conductive element is disposed within the passive component and electrically connected to the conductive structure,

and wherein the conductive element has a first portion within the electronic component, and the first portion is tapered toward the first surface of the electronic component,

and wherein the conductive element has a second portion within the passive component, and a sidewall of the first portion is substantially aligned with a sidewall of the second portion in a cross-sectional view, and

wherein a thickness of the second portion is greater than a thickness of the first portion along a direction from the first surface to the second surface of the electronic component.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: FANG, HSU-NAN
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 056645/0121 →
Continuity (1)
Related Publication 20220415799A1 · Dec 29, 2022
References Cited (7)
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Cited By (1)
US 12,557,704