Semiconductor devices
Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.
1. A semiconductor device comprising:
a substrate comprising a trench;
a first channel pattern and a second channel pattern on the substrate, the first channel pattern and the second channel pattern being separated by the trench and spaced apart from each other in a first direction, each of the first channel pattern and the second channel pattern including a plurality of semiconductor patterns that are spaced apart from each other and are stacked in a vertical direction;
a device isolation layer in the trench;
a first gate electrode on the first channel pattern, a second gate electrode on the second channel pattern, and a third gate electrode on the device isolation layer, the first, third, and second gate electrodes being arranged in the first direction and extending in a second direction intersecting the first direction; and
a first gate spacer on a first sidewall of the first gate electrode and a second gate spacer on a second sidewall of the second gate electrode,
wherein the first gate spacer covers sidewalls of the plurality of semiconductor patterns of the first channel pattern,
wherein the second gate spacer covers sidewalls of the plurality of semiconductor patterns of the second channel pattern, and
wherein a width of the device isolation layer in the first direction is greater than respective pitches of the first and third gate electrodes and the second and third gate electrodes.
2. The semiconductor device of claim 1 , wherein a first pitch between the first gate electrode and the third gate electrode is substantially equal to a second pitch between the third gate electrode and the second gate electrode.
3. The semiconductor device of claim 1 , wherein the plurality of semiconductor patterns of the first channel pattern protrudes beyond the first sidewall of the first gate electrode toward the third gate electrode.
4. The semiconductor device of claim 1 , wherein the plurality of semiconductor patterns of the second channel pattern protrudes beyond the second sidewall of the second gate electrode toward the third gate electrode.
5. The semiconductor device of claim 1 , wherein the first gate spacer extends from the first sidewall of the first gate electrode toward the device isolation layer.
6. The semiconductor device of claim 1 , wherein the second gate spacer extends from the second sidewall of the second gate electrode toward the device isolation layer.
7. The semiconductor device of claim 1 , wherein the third gate electrode is between the first gate spacer and the second gate spacer.
8. The semiconductor device of claim 1 , further comprising:
a first gate dielectric pattern between the first gate electrode and the first channel pattern,
wherein the first gate dielectric pattern between neighboring ones of the plurality of semiconductor patterns of the first channel pattern includes a third sidewall covered by the first gate spacer.
9. The semiconductor device of claim 8 , further comprising:
a second gate dielectric pattern between the second gate electrode and the second channel pattern,
wherein the second gate dielectric pattern between neighboring ones of the plurality of semiconductor patterns of the second channel pattern includes a fourth sidewall covered by the second gate spacer.
10. The semiconductor device of claim 1 , wherein the substrate includes a first logic cell region on which the first channel pattern is and a second logic cell region on which the second channel pattern is, and
wherein the first logic cell region and the second logic cell region are separated by the trench.