Ion implantation of nanostructures for nano-FET
A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.
1. A method comprising:
forming a stack of alternating layers of a first semiconductor material and a second semiconductor material over a substrate;
forming a dummy gate structure over the stack;
implanting first dopants in a first layer of the stack adjacent the dummy gate structure, the first dopants extending under the dummy gate structure;
removing portions of the first layer to expose portions of a second layer of the stack, a first channel portion of the first layer remaining under the dummy gate structure, wherein remaining portions of the first dopants in the first channel portion form a first doped channel junction, wherein the first layer and the second layer are layers of the first semiconductor material;
implanting second dopants in the second layer of the stack adjacent the dummy gate structure, the second dopants extending under the dummy gate structure, the first dopants and the second dopants having a same conductivity type;
removing portions of the second layer of the stack, a second channel portion of the second layer remaining under the dummy gate structure, wherein remaining portions of the second dopants in the second channel portion form a second doped channel junction; and
forming a source/drain region contacting the first channel portion and the second channel portion.
2. The method of claim 1 , wherein a width of the first channel junction is different than a width of the second channel junction.
3. The method of claim 1 , further comprising:
replacing the dummy gate structure with a replacement gate structure, wherein the replacement gate structure overlaps the first dopants in the first channel portion.
4. The method of claim 3 , further comprising:
exposing a third layer of the stack, the third layer being a layer of the first semiconductor material, wherein after replacing the dummy gate structure, the third layer lacks a doped channel junction.
5. The method of claim 4 , wherein the third layer is between the first layer and the second layer.
6. The method of claim 4 , wherein the third layer is below the first layer and the second layer.
7. The method of claim 1 , further comprising:
exposing a third layer of the stack, the third layer being a layer of the first semiconductor material; and
removing portions of the third layer, a third channel portion of the third layer remaining under the dummy gate structure, the third channel portion being free of the first dopants and the second dopants.
8. The method of claim 1 , wherein the first doped channel junction is wider than the second doped channel junction.
9. The method of claim 1 , wherein the first doped channel junction is narrower than the second doped channel junction.
10. A method comprising:
forming a stack of alternating layers of a first semiconductor material and a second semiconductor material over a substrate, the stack including a first layer and a second layer of the first semiconductor material, the first layer being over the second layer;
forming a dummy gate structure over the stack;
implanting first dopants of a first conductivity type in the first layer of the stack adjacent the dummy gate structure to form a first doped portion, the first doped portion extending under the dummy gate structure;
removing portions of first doped portion adjacent the dummy gate structure, a remaining portion of the first doped portion forming a first doped channel junction;
exposing the second layer of the stack adjacent the dummy gate structure;
implanting second dopants of the first conductivity type in the second layer of the stack adjacent the dummy gate structure to form a second doped portion, the second doped portion extending under the dummy gate structure;
removing portions of second doped portion adjacent the dummy gate structure, a remaining portion of the second doped portion forming a second doped channel junction, wherein a lateral dimension of the first doped channel junction is different than a lateral dimension of the second doped channel junction; and
forming a source/drain region adjacent the first doped channel junction and second doped channel junction.
11. The method of claim 10 , wherein the stack comprises a third layer between the first layer and the second layer, wherein the third layer being of the second semiconductor material, wherein exposing the second layer comprises removing portions of the third layer, further comprising:
recessing the third layer from sidewalls of the first layer to form a recess;
after recessing the third layer, forming an inner spacer layer along sidewalls of remaining portions of the first layer, the second layer, and the third layer, wherein the inner spacer layer as formed is free of the first dopants and the second dopants;
after forming the inner spacer layer, etching the inner spacer layer to form an inner spacer in the recess; and
after etching the inner spacer layer, replacing the dummy gate structure and the remaining portions of the third layer with a replacement gate structure, wherein after replacing the dummy gate structure, the inner spacer comprises the first dopants or the second dopants.
12. The method of claim 11 , wherein a peak concentration of the first dopants or the second dopants in the inner spacer is along an interface with the replacement gate structure.
13. The method of claim 10 , wherein the first dopants are different species than the second dopants.
14. The method of claim 10 , wherein both implanting the first dopants and implanting the second dopants comprise performing an angled implant with a tilt between about 3 degrees to 15 degrees.
15. A method comprising:
forming a stack of alternating layers of a first semiconductor material and a second semiconductor material over a substrate;
forming a gate structure over the stack;
patterning the stack to form a plurality of nanostructures under the gate structure, wherein the plurality of nanostructures comprises a plurality of first nanostructures of the first semiconductor material and a plurality of second nanostructures of the second semiconductor material, wherein patterning comprises performing a plurality of cycles, wherein each cycle comprises:
exposing an upper surface of a first one of the plurality of first nanostructures;
doping the first one of the plurality of first nanostructures to form a doped region; and
removing portions of the doped region of the first one of the plurality of first nanostructures, wherein remaining portions of the first one of the plurality of first nanostructures forms a first channel structure, wherein remaining portions of the doped region form a doped channel junction; and
forming a source/drain region adjacent the doped channel junction.
16. The method of claim 15 , wherein the plurality of first nanostructures comprises an upper nanostructure and a lower nanostructure, wherein a width of the doped channel junction in the upper nanostructure is different than a width of the doped channel junction in the lower nanostructure.
17. The method of claim 16 , wherein the width of the doped channel junction in the upper nanostructure is less than the width of the doped channel junction in the lower nanostructure.
18. The method of claim 16 , wherein the width of the doped channel junction in the upper nanostructure is greater than the width of the doped channel junction in the lower nanostructure.
19. The method of claim 15 , wherein the doped channel junction extends under the gate structure.
20. The method of claim 15 , further comprising:
prior to forming the source/drain region, recessing sidewalls of the plurality of second nanostructures to form recesses;
prior to forming the source/drain region, forming inner spacers in the recesses;
replacing the gate structure with a replacement gate structure; and
diffusing dopants into the inner spacers along an interface between the inner spacers and the replacement gate structure.