Methods for forming three-dimensional memory devices
In an example, a method for forming a three-dimensional (3D) memory device is disclosed. A semiconductor layer is formed. A memory stack on the semiconductor is formed. A channel structure extending through the memory stack and the semiconductor layer is formed. An end of the channel structure abutting the semiconductor layer is exposed. A portion of the channel structure abutting the semiconductor layer is replaced with a semiconductor plug.
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a semiconductor layer;
forming a memory stack on the semiconductor layer;
forming a channel structure extending through the memory stack and the semiconductor layer;
exposing an end of the channel structure abutting the semiconductor layer; and
replacing a portion of the channel structure abutting the semiconductor layer with a semiconductor plug.
2. The method of claim 1 , further comprising:
forming a sacrificial layer on a carrier substrate, wherein the semiconductor layer is formed on the sacrificial layer; and
removing the carrier substrate and the sacrificial layer to expose the end of the channel structure abutting the semiconductor layer.
3. The method of claim 1 , further comprising forming a source contact connected to the semiconductor layer after replacing the portion of the channel structure abutting the semiconductor layer with the semiconductor plug.
4. The method of claim 3 , wherein
the semiconductor layer is an N-type doped semiconductor layer; and
the source contact and the memory stack are disposed at opposite sides of the N-type doped semiconductor layer, and the source contact extends into the N-type doped semiconductor layer and is in contact with the N-type doped semiconductor layer.
5. The method of claim 3 , wherein
the semiconductor layer is a P-type doped semiconductor layer comprising an N-well;
the source contact and the memory stack are disposed at opposite sides of the P-type doped semiconductor layer; and
the source contact comprises a first source contact and a second source contact, wherein the first source contact extends into the P-type doped semiconductor layer and is directly in contact with the P-type doped semiconductor layer, and the second source contact extends into the N-well and is directly in contact with the N-well.
6. The method of claim 5 , further comprising doping, with an N-type dopant, a part of the P-type doped semiconductor layer to form the N-well arranged in the P-type doped semiconductor layer after forming the P-type doped semiconductor layer.
7. The method of claim 1 , wherein forming the memory stack comprises:
forming a dielectric stack comprising interleaved stack dielectric layers and stack sacrificial layers on the semiconductor layer;
etching an opening extending through the dielectric stack, stopping at the semiconductor layer; and
replacing the stack sacrificial layers with stack conductive layers through the opening to form the memory stack.
8. The method of claim 1 , wherein
the channel structure comprises a memory film and a semiconductor channel; and
replacing the portion of the channel structure abutting the semiconductor layer with the semiconductor plug comprises:
etching a portion of the memory film abutting the semiconductor layer to form a recess surrounding a portion of the semiconductor channel;
doping the portion of the semiconductor channel exposed by the recess; and
depositing polysilicon into the recess to form the semiconductor plug surrounding and in contact with the portion of the semiconductor channel.
9. The method of claim 3 , further comprising:
forming an interconnect layer in contact with the source contact; and
forming a contact through the semiconductor layer and in contact with the interconnect layer, the semiconductor layer being connected to the contact through the source contact and the interconnect layer.
10. A method for forming a three-dimensional (3D) memory device, comprising:
doping, with a dopant, a device layer of a silicon on insulator (SOI) wafer comprising a handle layer, a buried oxide layer, and the device layer to form a doped device layer;
forming a memory stack on the doped device layer;
forming a channel structure extending through the memory stack and the doped device layer;
removing the handle layer and the buried oxide layer of the SOI wafer to expose an end of the channel structure; and
replacing a portion of the channel structure abutting the doped device layer with a semiconductor plug.
11. The method of claim 10 , further comprising forming a source contact connected to the doped device layer after replacing the portion of the channel structure abutting the doped device layer with the semiconductor plug.
12. The method of claim 11 , wherein
the dopant is an N-type dopant; and
the source contact and the memory stack are disposed at opposite sides of the doped device layer, and the source contact extends into the doped device layer and is in contact with the doped device layer.
13. The method of claim 11 , wherein
the dopant is a P-type dopant;
the doped device layer comprises an N-well;
the source contact and the memory stack are disposed at opposite sides of the doped device layer; and
the source contact comprises a first source contact and a second source contact, wherein the first source contact extends into the doped device layer and is directly in contact with the doped device layer, and the second source contact extends into the N-well and is directly in contact with the N-well.
14. The method of claim 13 , further comprising doping, with an N-type dopant, a part of the doped device layer to form the N-well arranged in the doped device layer after doping the device layer to form the doped device layer.
15. The method of claim 10 , wherein forming the memory stack on the doped device layer comprises:
forming a dielectric stack comprising interleaved stack dielectric layers and stack sacrificial layers on the doped device layer;
etching an opening extending through the dielectric stack, stopping at the doped device layer; and
replacing the stack sacrificial layers with stack conductive layers through the opening to form the memory stack.
16. The method of claim 10 , wherein
the channel structure comprises a memory film and a semiconductor channel; and
replacing the portion of the channel structure abutting the doped device layer with the semiconductor plug comprises:
etching a portion of the memory film abutting the doped device layer to form a recess surrounding a portion of the semiconductor channel;
doping the portion of the semiconductor channel exposed by the recess; and
depositing polysilicon into the recess to form the semiconductor plug surrounding and in contact with the portion of the semiconductor channel.
17. The method of claim 11 , further comprising:
forming an interconnect layer in contact with the source contact; and
forming a contact through the doped device layer and in contact with the interconnect layer, the doped device layer being connected to the contact through the source contact and the interconnect layer.
18. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first wafer comprising:
a first substrate, and
a peripheral circuit on the first substrate;
forming a second wafer comprising:
a second substrate,
a semiconductor layer above the second substrate,
a memory stack comprising interleaved layers of stack dielectric layers and stack conductive layers above the semiconductor layer, and
a channel structure extending through the memory stack and the semiconductor layer;
bonding the first wafer and the second wafer in a face-to-face manner, the memory stack being arranged above the peripheral circuit;
removing the second substrate to expose an upper end of the channel structure; and
replacing a portion of the channel structure abutting the semiconductor layer with a semiconductor plug.
19. The method of claim 18 , further comprising prior to bonding the first wafer and the second wafer, forming an insulating structure extending vertically through the memory stack.
20. The method of claim 18 , wherein the semiconductor layer comprises an N-type doped semiconductor layer or a P-type doped semiconductor layer.