Level shifting in all levels programming of a memory device in a memory sub-system
Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.
1. A memory device comprising:
a memory array comprising a plurality of memory cells configured as a multi-level cell (MLC) memory; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a set of memory cells of the memory array to be programmed during a programming operation;
causing, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the first programming pulse programs each programming level of the set of programming levels associated with the set of memory cells;
performing a program verify operation corresponding to the first programming level;
comparing a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied; and
executing a level shifting operation in response to the condition being satisfied, wherein the level shifting operation causes a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted.
2. The memory device of claim 1 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is lower than the first programming level.
3. The memory device of claim 2 , the operations further comprising causing in view of the designation associated with the memory cell, at a second time during the program operation, the first bitline voltage level of [a] the first bitline corresponding to the memory cell to be toggled with a second bitline voltage level of a second bitline corresponding to a set of memory cells to be programmed to the second programming level.
4. The memory device of claim 2 , wherein the condition is satisfied if the threshold voltage of the memory cell is greater than a first program verify voltage level and less than a second program verify voltage level of the one or more program verify voltage levels of the program verify operation.
5. The memory device of claim 4 , wherein the second programming level is one programming level lower than the first programming level.
6. The memory device of claim 2 , wherein the condition is satisfied if the threshold voltage of the memory cell is greater than a first program verify voltage level and a second program verify voltage level and less than a third program verify voltage level of the one or more program verify voltage levels of the program verify operation.
7. The memory device of claim 6 , wherein the second programming level is more than one programming level lower than the first programming level.
8. A method comprising:
identifying a set of memory cells of a memory device to be programmed during a programming operation;
causing, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the first programming pulse programs each programming level of the set of programming levels associated with the set of memory cells;
performing a first program verify operation associated with the first programming level, wherein first program verify operation comprises comparing a threshold voltage of the memory cell to a first program verify voltage level and a second program verify voltage level to determine whether a first condition of a plurality of conditions is satisfied;
performing a second program verify operation associated with a programming level adjacent to the first programming level, wherein second program verify operation comprises comparing the threshold voltage of the memory cell to a third program verify voltage level and a fourth program verify voltage level to determine whether a second condition of the plurality of conditions is satisfied; and
executing one of a first level shifting operation in response to the first condition being satisfied or an up-level shifting operation in response to the second condition being satisfied, wherein the first level shifting operation and the up-level shifting operation cause a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted.
9. The method of claim 8 , wherein the first condition is satisfied when the threshold voltage of the memory cell is greater than the first program verify voltage level and less than the second program verify voltage level.
10. The method of claim 9 , wherein the first level shifting operation comprises updating a logical designation associated with the memory cell in a status register to cause, at a second time during the program operation, the first bitline voltage level of the first bitline corresponding to the memory cell to be toggled with a second bitline voltage level of a second bitline corresponding to a set of memory cells to be programmed to a second programming level, wherein the second programming level is lower than the first programming level.
11. The method of claim 10 , further comprising:
toggling the first bitline voltage level of the first bitline corresponding to the memory cell and the second bitline voltage level of the second bitline corresponding to the set of memory cells to be programmed to the second programming level from approximately zero volts to a higher voltage level.
12. The method of claim 8 , wherein the second condition is satisfied when the threshold voltage of the memory cell is greater than the third program verify voltage level and less than the fourth program verify voltage level.
13. The method of claim 12 , wherein the up-level shifting operation comprises updating a logical designation associated with the memory cell in a status register to cause, at a second time during the program operation, the first bitline voltage level of the first bitline corresponding to the memory cell to be toggled with a second bitline voltage level of a second bitline corresponding to a set of memory cells to be programmed to a second programming level, wherein the second programming level is higher than the first programming level.
14. A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a set of memory cells of the memory array to be programmed during a programming operation;
causing, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the set of memory cells to be programmed to a first programming level of a set of programming levels, wherein the first programming pulse programs each programming level of the set of programming levels associated with the set of memory cells;
performing a program verify operation corresponding to a second programming level, wherein the second programming level is lower than the first programming level;
comparing a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied; and
executing a level shifting operation in response to the condition being satisfied, wherein the level shifting operation causes a first bitline voltage level associated with a first bitline corresponding to the memory cell to be adjusted.
15. The memory device of claim 14 , wherein executing the level shifting operation comprises logically shifting a designation associated with the memory cell to a third programming level that is higher than the first programming level.
16. The memory device of claim 15 , the operations further comprising causing in view of the designation associated with the memory cell, at a second time during the program operation, the first bitline voltage level of the first bitline corresponding to the memory cell to be toggled with a second bitline voltage level of a second bitline corresponding to a set of memory cells to be programmed to the third programming level.
17. The memory device of claim 15 , wherein the condition is satisfied if the threshold voltage of the memory cell is greater than a first program verify voltage level and less than a second program verify voltage level of the one or more program verify voltage levels of the program verify operation, wherein the first program verify voltage level is less than the second program verify voltage level.
18. The memory device of claim 17 , wherein the third programming level is more than one programming level higher than the first programming level.
19. The memory device of claim 15 , wherein the condition is satisfied if the threshold voltage of the memory cell is greater than a first program verify voltage level and a second program verify voltage level and less than a third program verify voltage level of the one or more program verify voltage levels of the program verify operation, wherein the first program verify voltage level is level is less than the second program verify voltage level, and wherein the second program verify voltage level is less than the third program verify voltage level.
20. The memory device of claim 19 , wherein the third programming level is one programming level higher than the first programming level.