Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.
1. An integrated circuit structure, comprising:
a semiconductor fin;
a gate structure over the semiconductor fin, the gate structure including a gate insulating layer thereon;
a conductive trench contact structure laterally spaced apart from the gate structure, the conductive trench contact structure including a trench insulating layer thereon;
a first dielectric etch stop layer directly on and continuous over the trench insulating layer and the gate insulating layer;
a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer;
an interlayer dielectric material on the second dielectric etch stop layer;
an opening in the interlayer dielectric material, in the second dielectric etch stop layer, in the first dielectric etch stop layer, and in the trench insulating layer; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive trench contact structure.
2. The integrated circuit structure of claim 1 , wherein the second dielectric etch stop layer comprises aluminum and oxygen.
3. The integrated circuit structure of claim 1 , wherein the first etch stop layer comprises nitrogen, silicon and hydrogen.
4. The integrated circuit structure of claim 1 , wherein the interlayer dielectric material comprises silicon, oxygen, carbon and hydrogen.
5. The integrated circuit structure of claim 1 , wherein the trench insulating layers comprise silicon carbide, and the gate insulating layers comprise silicon nitride.
6. The integrated circuit structure of claim 1 , further comprising:
a dielectric spacer laterally between the gate structure and the conductive trench contact structure, wherein the first dielectric etch stop layer is directly on the dielectric spacer.
7. The integrated circuit structure of claim 1 , wherein the conductive structure includes an upper conductive line and a lower conductive via.
8. An integrated circuit structure, comprising:
a discrete three-dimensional semiconductor body having a channel region;
a gate structure completely surrounding the channel region of the discrete three-dimensional semiconductor body, the gate structure including a gate insulating layer thereon;
a conductive trench contact structure laterally spaced apart from the gate structure, the conductive trench contact structure including a trench insulating layer thereon;
a first dielectric etch stop layer directly on and continuous over the trench insulating layer and the gate insulating layer;
a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer;
an interlayer dielectric material on the second dielectric etch stop layer;
an opening in the interlayer dielectric material, in the second dielectric etch stop layer, in the first dielectric etch stop layer, and in the trench insulating layer; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive trench contact structure.
9. The integrated circuit structure of claim 8 , wherein the second dielectric etch stop layer comprises aluminum and oxygen.
10. The integrated circuit structure of claim 8 , wherein the first etch stop layer comprises nitrogen, silicon and hydrogen.
11. The integrated circuit structure of claim 8 , wherein the interlayer dielectric material comprises silicon, oxygen, carbon and hydrogen.
12. The integrated circuit structure of claim 8 , wherein the trench insulating layers comprise silicon carbide, and the gate insulating layers comprise silicon nitride.
13. The integrated circuit structure of claim 8 , further comprising:
a dielectric spacer laterally between the gate structure and the conductive trench contact structure, wherein the first dielectric etch stop layer is directly on the dielectric spacer.
14. The integrated circuit structure of claim 8 , wherein the conductive structure includes an upper conductive line and a lower conductive via.
15. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor fin or a discrete three-dimensional semiconductor body having a channel region;
a gate structure over the semiconductor fin or completely surrounding the channel region of the discrete three-dimensional semiconductor body, the gate structure including a gate insulating layer thereon;
a conductive trench contact structure laterally spaced apart from the gate structure, the conductive trench contact structure including a trench insulating layer thereon;
a first dielectric etch stop layer directly on and continuous over the trench insulating layer and the gate insulating layer;
a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer;
an interlayer dielectric material on the second dielectric etch stop layer;
an opening in the interlayer dielectric material, in the second dielectric etch stop layer, in the first dielectric etch stop layer, and in the trench insulating layer; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive trench contact structure.
16. The computing device of claim 15 , wherein the integrated circuit structure comprises the semiconductor fin.
17. The computing device of claim 15 , wherein the integrated circuit structure comprises the discrete three-dimensional semiconductor body.
18. The computing device of claim 15 , further comprising:
a memory coupled to the board.
19. The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
20. The computing device of claim 15 , wherein the component is a packaged integrated circuit die.