System, apparatus and method for loose lock-step redundancy power management
A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
1. An apparatus comprising:
a first core comprising:
a fetch circuit to fetch instructions;
a decode circuit to decode the instructions;
an execution circuit to execute arithmetic and logic operations;
a second core comprising:
a second fetch circuit to fetch instructions;
a second decode circuit to decode the instructions;
a second execution circuit to execute arithmetic and logic operations,
wherein in a first mode the first core and the second core are to operate at a common frequency, and in a second mode the first core and the second core are to operate at independent frequencies;
memory to store a first indicator, the first indicator to have a first value to indicate that the first core and a second core are to execute in the first mode to redundantly execute a first task at the common frequency; and
a controller to cause the first core and the second core to operate in the second mode at the independent frequencies, and thereafter operate in the first mode at the common frequency to redundantly execute the first task based at least in part on the first value of the first indicator.
2. The apparatus of claim 1 , further comprising a cluster comprising the first core and the second core.
3. The apparatus of claim 2 , further comprising a third core, wherein the controller is to cause the third core to execute a second task different than the first task.
4. The apparatus of claim 3 , wherein the third core is heterogeneous to the first core.
5. The apparatus of claim 3 , wherein the controller is to cause the third core to execute the second task while the first core and the second core execute the first task redundantly.
6. The apparatus of claim 1 , wherein the controller is to cause the first core and the second core to operate at the independent frequencies based at least in part on a second value of the first indicator.
7. The apparatus of claim 1 , wherein the apparatus is to perform a functional safety application in the first mode.
8. The apparatus of claim 1 , wherein the controller comprises a power controller.
9. The apparatus of claim 8 , wherein the power controller is to cause at least the first core to perform dynamic frequency scaling.
10. The apparatus of claim 8 , wherein the power controller is to cause at least the first core to enter into a retention mode in which a retention voltage is provided to at least the first core.
11. The apparatus of claim 1 , wherein the first core is to execute main code and the second core is to execute checker code.
12. The apparatus of claim 1 , further comprising a redundancy circuit to compare a first result of the redundant execution of the first task on the first core to a second result of the redundant execution of the first task on the second core, and to raise an error if the first result does not at least substantially match the second result.
13. The apparatus of claim 1 , wherein the controller is to set the common frequency to be a highest of the independent frequencies.
14. A system on chip comprising:
a central processing circuit (CPU) comprising:
a first core;
a second core, wherein the first core and the second core are to execute a first task redundantly;
a graphics processing circuit (GPU) coupled to the CPU, the GPU comprising at least one graphics engine to perform graphics processing;
memory to store a first indicator, the first indicator to have a first value to indicate that the first core and the second core are to redundantly execute the first task; and
a controller to cause the first core and the second core to operate at independent frequencies, and thereafter to operate at a common frequency to redundantly execute the first task based at least in part on the first value of the first indicator.
15. The system on chip of claim 14 , wherein the controller is to cause the first core and the second core to operate at the independent frequencies based at least in part on a second value of the first indicator.
16. The system on chip of claim 14 , wherein the second core is to redundantly execute the first task within 1 to 10,000 execution cycles of the first task by the first core.
17. The system on chip of claim 14 , further comprising a redundancy circuit to compare a first result of the redundant execution of the first task on the first core to a second result of the redundant execution of the first task on the second core.
18. An apparatus comprising:
a first core;
a second core;
a storage to store a first indicator, wherein the first indicator is to indicate that the first core and the second core are to redundantly execute a first task when the first indicator has a first value; and
a controller coupled to the storage, wherein the controller is to cause the first core and the second core to operate with independent core operation and thereafter to operate with redundancy in lockstep operation,
wherein, in the redundancy in lockstep operation the first core and the second core are to operate at a common frequency to redundantly execute the first task based at least in part on the first value of the first indicator, and
wherein, in the independent core operation the first core and the second core are to operate at independent frequencies based at least in part on a second value of the first indicator.
19. The apparatus of claim 18 , wherein the controller is to cause the first core and the second core to operate at the common frequency that is a highest of the independent frequencies.
20. The apparatus of claim 18 , further comprising a security processor.