Semiconductor device
A semiconductor device includes a first voltage generating circuit configured to output a first voltage based on temperature; an analog-to-digital converter configured to convert the first voltage into a temperature code; a code conversion logic configured to output an offset code and a level code of a temperature section which the temperature belongs among temperature sections based on the temperature code; an offset voltage generating circuit configured to output an offset voltage based on the offset code; a second voltage generating circuit configured to output a second voltage having a constant value within a temperature section based on the level code; and a temperature compensation voltage generating circuit configured to receive the first voltage, the second voltage, the offset voltage, and a feedback voltage and output a temperature compensation voltage, the feedback voltage based on the first voltage, the second voltage, and the offset voltage.
1. A semiconductor device, comprising:
a first voltage generating circuit configured to output a first voltage based on a temperature;
an analog-to-digital converter configured to convert the first voltage into a temperature code;
a code conversion logic configured to output an offset code and a level code of a temperature section to which the temperature belongs among a plurality of temperature sections based on the temperature code;
an offset voltage generating circuit configured to output an offset voltage based on the offset code;
a second voltage generating circuit configured to output a second voltage having a constant value within a temperature section to which the temperature belongs among the plurality of temperature sections based on the level code; and
a temperature compensation voltage generating circuit configured to
receive the first voltage, the second voltage, the offset voltage, and a feedback voltage, the feedback voltage being based on the first voltage, the second voltage, and the offset voltage, and
output a temperature compensation voltage.
2. The semiconductor device of claim 1 , wherein a number of the plurality of temperature sections is based on a resolution of the analog-to-digital converter.
3. The semiconductor device of claim 1 , wherein
a number of bits of the offset code is based on a resolution of the offset voltage generating circuit, and
the number of bits of the level code is based on a resolution of the second voltage generating circuit.
4. The semiconductor device of claim 1 , wherein the temperature compensation voltage generating circuit is configured to
receive the first voltage, the second voltage, the offset voltage, the feedback voltage, and an adjustment code, and
output the temperature compensation voltage based on the adjustment code.
5. The semiconductor device of claim 1 , wherein the second voltage in each of the plurality of temperature sections is equal to a first voltage at a start point of each of the plurality of temperature sections.
6. The semiconductor device of claim 1 , wherein
the offset voltage generating circuit is configured to output the offset voltage based on a value obtained by adding a reference code to the offset code, and
the reference code corresponds to the temperature compensation voltage at a highest temperature in the plurality of temperature sections.
7. The semiconductor device of claim 1 , wherein the second voltage generating circuit includes variable resistor devices configured to have a resistor value based on the level code.
8. The semiconductor device of claim 7 , wherein the second voltage generating circuit includes
a decoder configured to receive the level code,
a plurality of resistors connected to each other in series, and
a plurality of transistors configured to receive an output value of the decoder.
9. The semiconductor device of claim 1 , wherein the temperature compensation voltage generating circuit includes
a first NMOS device configured to receive the first voltage,
a second NMOS device configured to receive the second voltage,
a third NMOS device configured to receive the offset voltage,
a fourth NMOS device configured to receive the feedback voltage,
a first current source configured to output a constant reference current, and
a second current source configured to output a compensation current by receiving an adjustment code.
10. The semiconductor device of claim 9 , wherein
the first NMOS device and the third NMOS device are connected to each other in parallel, and
the second NMOS device and the fourth NMOS device are connected to each other in parallel.
11. The semiconductor device of claim 9 , wherein an intensity ratio between a current flowing through the first NMOS device and the second NMOS device and a current flowing through the third NMOS device and the fourth NMOS device is based on the adjustment code.
12. The semiconductor device of claim 9 , wherein
each of the first NMOS device and the second NMOS device has a first width, and
each of the third NMOS device and the fourth NMOS device has a second width.
13. The semiconductor device of claim 12 , wherein a temperature compensation voltage is based on a ratio between the first width and the second width.
14. A semiconductor device, comprising:
a cell region including a plurality of memory cells; and
a peripheral circuit region including peripheral circuits driving the cell region, the peripheral circuit region including
a first voltage generating circuit configured to output a first voltage based on a temperature;
an analog-to-digital converter configured to convert the first voltage into a temperature code;
an offset voltage generating circuit configured to output an offset voltage of a temperature section to which the temperature belongs among a plurality of temperature sections based on the temperature code;
a second voltage generating circuit configured to output a second voltage having a constant value within a temperature section to which the temperature belongs among the plurality of temperature sections based on the temperature code; and
a temperature compensation voltage generating circuit configured to receive the first voltage, the second voltage, the offset voltage, and a feedback voltage and to output a temperature compensation voltage, the feedback voltage being based on the first voltage, the second voltage, and the offset voltage.
15. The semiconductor device of claim 14 , wherein peripheral circuit region is configured to determine a level of a voltage input to the cell region based on the temperature compensation voltage.
16. The semiconductor device of claim 14 , wherein
the peripheral circuit region includes a row decoder connected to the cell region through a plurality of word lines, a plurality of ground select lines, a plurality of string select lines, and a common source line, and
the row decoder is configured to determine a level of a voltage input to at least one of the plurality of word lines, the plurality of ground select lines, the plurality of string select lines, and the common source line based on the temperature compensation voltage.
17. The semiconductor device of claim 16 , wherein the row decoder is configured to determine a level of at least one of a program voltage input to a selected word line connected to a selected memory cell among the plurality of memory cells during a program operation and a pass voltage input to non-selected word lines connected to memory cells other than the selected memory cell among the plurality of memory cells, with reference to the temperature compensation voltage.
18. The semiconductor device of claim 16 , wherein the row decoder is configured to determine a level of at least one of a read voltage input to a selected word line connected to a selected memory cell among the plurality of memory cells during a read operation and a pass voltage input to non-selected word lines connected to memory cells other than the selected memory cell among the plurality of memory cells, with reference to the temperature compensation voltage.
19. The semiconductor device of claim 14 , wherein the temperature compensation voltage generating circuit includes a first NMOS device configured to receive the first voltage, a second NMOS device configured to receive the second voltage, a third NMOS device configured to receive the offset voltage, a fourth NMOS device configured to receive the feedback voltage, and a current source configured to output a current to the third NMOS and the fourth NMOS devices by receiving an adjustment code.
20. A semiconductor device, comprising:
a voltage generating circuit configured to output an offset voltage corresponding to each of a plurality of temperature sections based on a first voltage, the first voltage based on a temperature of an integrated circuit, and the voltage generating circuit configured to output a second voltage which is constant in each of the plurality of temperature sections based on the first voltage; and
a temperature compensation voltage generating circuit configured to receive the first voltage, the second voltage, the offset voltage, and a feedback voltage and to output a temperature compensation voltage, the feedback voltage being based on the first voltage, the second voltage, and the offset voltage.