Buried power rail formation for vertical field effect transistors
A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.
1. A semiconductor structure comprising:
a channel fin extending vertically above a bottom source/drain region;
a protective liner along opposite sidewalls of the bottom source/drain region, the bottom source/drain region located above a semiconductor layer in contact with a first portion of an inner spacer;
a first metal layer located between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covering a top surface of the first metal layer and the second portion of the inner spacer substantially covering a bottom surface of the first metal layer for providing a buried power rail; and
a shallow trench isolation region above an exposed portion of the first metal layer, the shallow trench isolation region being adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.
2. The semiconductor structure of claim 1 , further comprising:
a bottom spacer above the shallow trench isolation region and above the bottom source/drain region, the bottom spacer disposed on a bottom portion of opposite sidewalls of the channel fin.
3. The semiconductor structure of claim 2 , further comprising:
a top source/drain region in contact with a top portion of the channel fin; and
a metal gate located around the channel fin, the metal gate being separated from the top source/drain region by a top spacer and from the bottom source/drain region by the bottom spacer, the metal gate and the top spacer being in contact with an adjacent interlevel dielectric layer.
4. The semiconductor structure of claim 3 , further comprising:
a top source/drain contact extending through the interlevel dielectric layer until an uppermost surface of the top source/drain region;
a bottom source/drain contact extending through the interlevel dielectric layer until an uppermost surface of the bottom source/drain region; and
a gate contact extending through the interlevel dielectric layer until an uppermost surface of the metal gate.
5. The semiconductor structure of claim 1 , further comprising:
a conductive via extending through the bottom source/drain region until a to portion of the first metal layer; and
a dielectric cap above the conductive via.
6. The semiconductor structure of claim 1 , wherein the first metal layer is composed of a low-resistance conductive material including at least one of ruthenium, tungsten and cobalt.
7. The semiconductor structure of claim 1 , wherein the protective liner comprises a conformally deposited liner material for protecting the bottom source/drain region.
8. The semiconductor structure of claim 1 , further comprising:
an isolation region located in a p-n boundary region, the isolation region separating adjacent bottom source/drain regions and extending through the semiconductor layer, the first portion of the inner spacer, the first metal layer and the second portion of the inner spacer until a top portion of a substrate disposed below the second portion of the inner spacer.
9. The semiconductor structure of claim 8 , wherein the isolation region further comprises:
a nitride liner; and
a dielectric fill layer disposed above the nitride liner.
10. A semiconductor structure comprising:
a first region including a first channel fin extending vertically above a first bottom source/drain region;
a second region including a second channel fin extending vertically above a second bottom source/drain region, the first region being separated from the second region by an isolation region;
a protective liner along opposite sidewalls of each of the first bottom source/drain region and the second bottom/source drain region, each of the first bottom source/drain region and the second bottom/source drain region located above a semiconductor layer in contact with a first portion of an inner spacer;
a first metal layer located between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covering a top surface of the first metal layer and the second portion of the inner spacer substantially covering a bottom surface of the first metal layer for providing a buried power rail; and
a shallow trench isolation region above an exposed portion of the first metal layer, the shallow trench isolation region being adjacent to the first portion of the inner spacer, the semiconductor layer, and each of the first bottom source/drain region and the bottom source/drain region.
11. The semiconductor structure of claim 10 , further comprising:
a bottom spacer above the shallow trench isolation region, the isolation region and above each of the first bottom source/drain region and the second bottom source/drain region, the bottom spacer disposed on a bottom portion of opposite sidewalls of each of the first channel fin and the second channel fin.
12. The semiconductor structure of claim 11 , further comprising:
a first top source/drain region in contact with a top portion of the first channel fin;
a second top source/drain region in contact with a top portion of the second channel fin; and
a metal gate located around each of the first channel fin and the second channel fin, the metal gate being separated from the first top source/drain region and the second top source/drain region by a top spacer and from the first bottom source/drain region and the second bottom source/drain region by the bottom spacer, the metal gate and the top spacer being in contact with an adjacent interlevel dielectric layer.
13. The semiconductor structure of claim 12 , further comprising:
a top source/drain contact extending through the interlevel dielectric layer until an uppermost surface of each of the first top source/drain region and the second top source/drain region;
a bottom source/drain contact extending through the interlevel dielectric layer until an uppermost surface of each of the first bottom source/drain region and the second bottom source/drain region; and
a gate contact extending through the interlevel dielectric layer until an uppermost surface of the metal gate.
14. The semiconductor structure of claim 10 , further comprising:
a conductive via extending through the first bottom source/drain region and the second bottom source/drain region until a top portion of the first metal layer; and
a dielectric cap above the conductive via.
15. The semiconductor structure of claim 10 , wherein the first metal layer is composed of a low-resistance conductive material including ruthenium.
16. The semiconductor structure of claim 10 , wherein the protective liner comprises a conformally deposited liner material for protecting the bottom source/drain region.
17. The semiconductor structure of claim 10 , wherein the isolation region is located in a p-n boundary region, the isolation region separating the first bottom source/drain region and the second bottom source/drain region and extending through the semiconductor layer, the first portion of the inner spacer, the first metal layer and the second portion of the inner spacer until a top portion of a substrate disposed below the second portion of the inner spacer.
18. The semiconductor structure of claim 17 , wherein the isolation region further comprises:
a nitride liner; and
a dielectric fill layer disposed above the nitride liner.
19. The semiconductor structure of claim 18 , wherein the nitride liner is composed of a silicon nitride material and the dielectric fill layer is composed of silicon dioxide.
20. The semiconductor structure of claim 10 , wherein the first region comprises a p-FET region and the second region comprises an n-FET region.