Memory device and method of operating the same
View Patent ↗A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.
1. A memory device, comprising:
a first mux transistor and a first control transistor coupled between a sense amplifier and ground, and commonly connected at a first node;
a first shared gate transistor connecting a first bit line to the first node;
a second shared gate transistor connecting a second bit line to the first node;
a first memory cell connected to the first bit line; and
a second memory cell connected to the second bit line, wherein the first memory cell and the second memory cell share a first word line transistor gated by a first word line.
2. The memory device of claim 1 , wherein the first shared gate transistor and the second shared gate transistor each have a gate terminal connected to a gate control line.
3. The memory device of claim 2 , further comprising a controller, during a read operation of the first memory cell, configured to:
activate the first word line;
activate the gate control line; and
activate a mux control line connected to a gate terminal of the first mux transistor.
4. The memory device of claim 3 , wherein the controller, during the read operation of the first memory cell, is further configured to deactivate a control line connected to a gate terminal of the first control transistor.
5. The memory device of claim 4 , further comprising:
a third memory cell connected to the first bit line;
a fourth memory cell connected to the second bit line, wherein the third memory cell and the fourth memory cell share a second word line transistor gated by a second word line.
6. The memory device of claim 5 , wherein the controller is configured to, during the read operation of the first memory cell, deactivate the second word line.
7. The memory device of claim 1 , wherein the first and second memory cells each comprise a storage unit including a resistor or a capacitor.
8. The memory device of claim 1 , further comprising:
a second mux transistor and a second control transistor coupled between the sense amplifier and ground, and commonly connected at a second node;
a third shared gate transistor connecting a third bit line to the second node;
a fourth shared gate transistor connecting a fourth bit line to the second node;
a third memory cell connected to the third bit line; and
a fourth memory cell connected to the fourth bit line, wherein the third memory cell and the fourth memory cell share a second word line transistor gated by the first word line.
9. The memory device of claim 8 , further comprising:
a fifth memory cell connected to the third bit line;
a sixth memory cell connected to the fourth bit line, wherein the fifth memory cell and the sixth memory cell share a third word line transistor gated by a second word line.
10. A memory device, comprising:
a first mux transistor and a first control transistor coupled between a sense amplifier and ground, and commonly connected at a first node;
a first shared gate transistor having its source/drain terminals configured to connect a first bit line to the first node;
a second shared gate transistor having its source/drain terminals configured to connect a second bit line to the first node;
a first memory cell connected to the first bit line; and
a second memory cell connected to the second bit line, wherein the first memory cell and the second memory cell share a first word line transistor gated by a first word line;
wherein the first shared gate transistor and the second shared gate transistor each have a gate terminal connected to a gate control line.
11. The memory device of claim 10 , further comprising a controller, during a read operation of the first memory cell, configured to:
activate the first word line;
activate the gate control line; and
activate a mux control line connected to a gate terminal of the first mux transistor.
12. The memory device of claim 11 , wherein the controller, during the read operation of the first memory cell, is further configured to deactivate a control line connected to a gate terminal of the first control transistor.
13. The memory device of claim 12 , further comprising:
a third memory cell connected to the first bit line; and
a fourth memory cell connected to the second bit line, wherein the third memory cell and the fourth memory cell share a second word line transistor gated by a second word line.
14. The memory device of claim 13 , wherein the controller is configured to, during the read operation of the first memory cell, deactivate the second word line.
15. The memory device of claim 10 , wherein the first and second memory cells each comprise a storage unit including a resistor or a capacitor.
16. The memory device of claim 10 , further comprising:
a second mux transistor and a second control transistor coupled between the sense amplifier and ground, and commonly connected at a second node;
a third shared gate transistor connecting a third bit line to the second node;
a fourth shared gate transistor connecting a fourth bit line to the second node;
a third memory cell connected to the third bit line; and
a fourth memory cell connected to the fourth bit line, wherein the third memory cell and the fourth memory cell share a second word line transistor gated by the first word line.
17. The memory device of claim 16 , further comprising:
a fifth memory cell connected to the third bit line; and
a sixth memory cell connected to the fourth bit line, wherein the fifth memory cell and the sixth memory cell share a third word line transistor gated by a second word line.
18. A memory device, comprising:
a first mux transistor and a first control transistor coupled between a sense amplifier and ground, and commonly connected at a first node;
a first shared gate transistor connecting a first bit line to the first node;
a second shared gate transistor connecting a second bit line to the first node;
a first memory cell connected to the first bit line;
a second memory cell connected to the second bit line, wherein the first memory cell and the second memory cell share a first word line transistor gated by a first word line;
a third memory cell connected to the first bit line; and
a fourth memory cell connected to the second bit line, wherein the third memory cell and the fourth memory cell share a second word line transistor gated by a second word line;
wherein the first shared gate transistor and the second shared gate transistor each have a gate terminal connected to a gate control line.
19. The memory device of claim 18 , wherein the first to fourth memory cells each comprise a storage unit including a resistor or a capacitor.
20. The memory device of claim 18 , further comprising a controller, during a read operation of the first memory cell, configured to:
activate the first word line;
activate the gate control line;
activate a mux control line connected to a gate terminal of the first mux transistor; and
deactivate a control line connected to a gate terminal of the first control transistor.