High speed interconnect symbol stream forward error-correction
Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.
1. An apparatus, comprising:
a transmitter; and
physical (PHY) layer circuitry for the transmitter, the PHY layer circuitry to:
encode symbols for a symbol stream;
interleave the symbols from the symbol stream to form interleaved forward error correction (FEC) blocks;
generate Reed Solomon (RS) parity symbols for the interleaved FEC blocks; and
generate a FEC symbol stream from the interleaved FEC blocks and the RS parity symbols.
2. The apparatus of claim 1 , the PHY layer circuitry to encode the symbols for the symbol stream with an 8b10b encoding scheme.
3. The apparatus of claim 1 , the PHY layer circuitry to:
interleave a number of even symbols from the symbol stream to form a first FEC block; and
interleave a number of odd symbols from the symbol stream to form a second FEC block.
4. The apparatus of claim 3 , the PHY layer circuitry to:
generate RS parity symbols for the first FEC block and the second FEC block;
interleave the RS parity symbols generated for the first FEC block with the RS parity symbols generated for the second FEC block; and
encode the interleaved RS parity symbols with an 8b10b encoding scheme.
5. The apparatus of claim 1 , wherein the RS parity symbols are generated based on an RS error-correction code having a Galois Fields (GF) of 2 m .
6. The apparatus of claim 1 , comprising processor circuitry communicatively coupled to the PHY layer circuitry to generate information for the symbol stream.
7. The apparatus of claim 1 , comprising a receiver and PHY layer circuitry for the receiver, the PHY layer circuitry for the receiver to:
receive a FEC symbol stream, wherein the FEC symbol stream comprises FEC blocks and RS parity symbols;
de-interleave the FEC blocks, based on the plurality of RS parity symbols, to form a symbol stream; and
decode link layer symbols from the symbol stream based on an 8b10b encoding scheme.
8. A method, comprising:
encoding symbols for a symbol stream;
interleaving symbols from the symbol stream to form interleaved forward error correction (FEC) blocks;
generating Reed Solomon (RS) parity symbols for the interleaved FEC blocks; and
generating a FEC symbol stream from the interleaved FEC blocks and the RS parity symbols.
9. The method of claim 8 , comprising encoding the symbols for the symbol stream with an 8b10b encoding scheme.
10. The method of claim 8 , comprising:
interleaving a number of even symbols from the symbol stream to form a first FEC block; and
interleaving a number of odd symbols from the symbol stream to form a second FEC block.
11. The method of claim 10 , comprising:
generating RS parity symbols for the first FEC block and the second FEC block;
interleaving the RS parity symbols generated for the first FEC block with the RS parity symbols generated for the second FEC block; and
encoding the interleaved RS parity symbols with an 8b10b encoding scheme.
12. The method of claim 8 , wherein the RS parity symbols are generated based on an RS error-correction code having a Galois Fields (GF) of 2 m .
13. The method of claim 8 , comprising retrieving information for the symbol stream from a memory unit or a storage device.
14. The method of claim 8 , comprising:
receiving a FEC symbol stream, wherein the FEC symbol stream comprises FEC blocks and RS parity symbols;
de-interleaving the FEC blocks, based on the plurality of RS parity symbols, to form a symbol stream; and
decoding link layer symbols from the symbol stream based on an 8b10b encoding scheme.
15. At least one non-transitory storage device comprising a plurality of instructions that in response to being executed by circuitry cause the circuitry to:
encode symbols for a symbol stream;
interleave symbols from the symbol stream to form interleaved forward error correction (FEC) blocks;
generate Reed Solomon (RS) parity symbols for the interleaved FEC blocks; and
generate a FEC symbol stream from the interleaved FEC blocks and the RS parity symbols.
16. The at least one storage device of claim 15 , comprising instructions that in response to be executed by the circuitry cause the circuitry to encode the symbols for the symbol stream with an 8b10b encoding scheme.
17. The at least one storage device of claim 15 , comprising instructions that in response to be executed by the circuitry cause the circuitry to:
interleave a number of even symbols from the symbol stream to form a first FEC block; and
interleave a number of odd symbols from the symbol stream to form a second FEC block.
18. The at least one storage device of claim 17 , comprising instructions that in response to be executed by the circuitry cause the circuitry to:
generate RS parity symbols for the first FEC block and the second FEC block;
interleave the RS parity symbols generated for the first FEC block with the RS parity symbols generated for the second FEC block; and
encode the interleaved RS parity symbols with an 8b10b encoding scheme.
19. The at least one storage device of claim 15 , wherein the RS parity symbols are generated based on an RS error-correction code having a Galois Fields (GF) of 2 m .
20. The at least one storage device of claim 15 , comprising instructions that in response to be executed by the circuitry cause the circuitry to generate information for the symbol stream or retrieve information for the symbol stream.