Integrated circuit structure
An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.
1. An integrated circuit structure, comprising:
a substrate comprising thereon a logic core circuit region and an embedded memory area;
a copper interconnect structure disposed on the substrate, wherein the copper interconnect structure comprises an uppermost copper layer covered by a dielectric stack comprising a silicon nitride cap layer, a lower dielectric layer on the silicon nitride cap layer, and an upper dielectric layer on the lower dielectric layer;
an aluminum pad layer disposed on the dielectric stack, wherein the aluminum pad layer comprises a first pad pattern within the logic core circuit region and a second pad pattern within the embedded memory area;
a passivation layer covering the first pad pattern within the logic core circuit region and the second pad pattern within the embedded memory area; and
an aluminum shield layer comprising aluminum routing patterns disposed directly above the embedded memory area and embedded between the lower dielectric layer and the upper dielectric layer, wherein the aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias, wherein the plurality of tungsten vias is embedded in the lower dielectric layer and the silicon nitride cap layer.
2. The integrated circuit structure according to claim 1 , wherein the first pad pattern and the second pad pattern respectively contact the uppermost copper layer and the aluminum shield layer at different horizontal levels.
3. The integrated circuit structure according to claim 1 , wherein the aluminum shield layer has a thickness that is thinner than that of the aluminum pad layer.
4. The integrated circuit structure according to claim 1 , wherein the upper dielectric layer covers the aluminum shield layer and is in direct contact with a sidewall and a top surface of the aluminum shield layer.
5. The integrated circuit structure according to claim 1 , wherein each of the plurality of tungsten vias has a width of about 0.3-0.8 micrometers.
6. The integrated circuit structure according to claim 5 , wherein the aluminum shield layer has a line width of about 0.5-2 micrometers and a space between adjacent two of the aluminum routing patterns of about 0.5-2 micrometers.
7. The integrated circuit structure according to claim 1 , wherein a top surface of the plurality of tungsten vias is coplanar with a top surface of the lower dielectric layer.
8. The integrated circuit structure according to claim 7 , wherein the lower dielectric layer comprises silicon oxide.
9. The integrated circuit structure according to claim 1 , wherein the aluminum pad layer is electrically connected to the metal layer through an aluminum via.
10. The integrated circuit structure according to claim 1 , wherein the passivation layer comprises a phosphorus silicate glass (PSG) layer and a silicon nitride layer.