IP Library Granted Patent US 12,283,607
Granted Patent B2
US 12,283,607 · App. 17/349,724 · Granted Apr 22, 2025

3D inductor design using bundle substrate vias

Inventors: Jonghae Kim (San Diego, CA); Je-Hsiung Lan (San Diego, CA); Ranadeep Dutta (Del Mar, CA)
Assignee: QUALCOMM Incorporated
H01L28/10H01F17/0006H01F27/2804H01L21/76898H01L23/481H01L23/66H01P3/08H01P11/003H01F2017/004H01L2223/6627H01L2223/6672
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Quick Facts
Patent No.
US 12,283,607
App. No.
17/349,724
Granted
Apr 22, 2025
Kind
B2
Abstract

A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

Claims (16)

1. A three dimensional (3D) inductor, comprising:

a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate, each micro-TSV having a diameter of less than twenty micrometers, the first plurality of micro-TSVs arranged in multiple columns and multiple rows, the first area of the substrate corresponding to a macro-TSV opening of the substrate having a diameter of more than eighty micrometers;

a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs; and

a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

2. The 3D inductor of claim 1 , in which a space between two micro-TSVs of the first plurality of micro-TSVs is less than a space between the first area of the substrate corresponding to a form factor of a macro-TSV and a second area of the substrate corresponding to the form factor of the macro-TSV.

3. The 3D inductor of claim 1 , in which the 3D inductor is integrated in an integrated passive device (IPD).

4. The 3D inductor of claim 3 , in which the IPD is integrated in an IPD filter die.

5. The 3D inductor of claim 4 , in which the IPD filter die is integrated in a radio frequency front-end (RFFE) module.

6. A method for fabricating a three dimensional (3D) inductor, the method comprising:

forming a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate, each micro-TSV having a diameter of less than twenty micrometers, the first plurality of micro-TSVs arranged in multiple columns and multiple rows, the first area of the substrate corresponding to a macro-TSV opening of the substrate;

depositing a first trace on a first surface of the substrate to contact a first end of the first plurality of micro-TSVs; and

depositing a second trace on a second surface of the substrate, opposite the first surface, to contact a second end, opposite the first end, of the first plurality of micro-TSVs.

7. The method of claim 6 , in which forming the first plurality of micro-TSVs comprises uniformly spacing the first plurality of micro-TSVs, in which a space between two micro-TSVs of the first plurality of micro-TSVs is less than a space between the first area of the substrate corresponding to a form factor of a macro-TSV and a second area of the substrate corresponding to the form factor of the macro-TSV.

8. The method of claim 6 , further comprising integrating the 3D inductor in an integrated passive device (IPD).

9. The method of claim 8 , further comprising integrating the IPD in an IPD filter die.

10. The method of claim 9 , further comprising integrating the IPD filter die in a radio frequency front-end (RFFE) module.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2021
From: KIM, JONGHAE; LAN, JE-HSIUNG; DUTTA, RANADEEP
To: QUALCOMM INCORPORATED
Reel/Frame 056620/0541 →
Continuity (1)
Related Publication 20220406882A1 · Dec 22, 2022
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