FinFET having a work function material gradient
A method includes forming a semiconductor fin; forming a gate dielectric layer over the semiconductor fin; depositing a first work function metal layer over the gate dielectric layer, the first work function metal layer having a first concentration of a work function material; depositing a second work function metal layer over the first work function metal layer, the second work function metal layer having a second concentration of the work function material, wherein the first concentration is higher than the second concentration; and forming a gate electrode over the second work function metal layer.
1. A method, comprising:
forming a semiconductor fin;
forming a gate dielectric layer over the semiconductor fin;
depositing a p-type work function metal layer over the gate dielectric layer;
depositing an n-type work function metal layer over the p-type work function metal layer; and
forming a gate electrode over the n-type work function metal layer, wherein a concentration of a work function material in the n-type work function metal layer increases from a first value to a peak value and then decreases from the peak value to a second value, and wherein the concentration of the work function material in the n-type work function metal layer at an interface of the gate electrode and the n-type work function metal layer has a first non-zero value lower than about 35%.
2. The method of claim 1 , wherein the work function material has a vacuum work function value smaller than about 4.4 eV.
3. The method of claim 1 , wherein forming the gate electrode is performed at a temperature in a range from about 250° C. to about 550° C.
4. The method of claim 1 , further comprising:
forming a liner lining a lower portion of a sidewall of the semiconductor fin; and
forming an isolation structure over the liner.
5. The method of claim 4 , wherein forming the gate dielectric layer comprises:
forming an interfacial layer lining an upper portion of the sidewall of the semiconductor fin and in contact with the liner; and
forming a high-k dielectric layer over the interfacial layer and in contact with the isolation structure.
6. The method of claim 1 , wherein the concentration of the work function material in the n-type work function metal layer at an interface of the p-type work function metal layer and the n-type work function metal layer has a second non-zero value lower than about 35%.
7. The method of claim 1 , wherein the gate electrode comprises tungsten.
8. The method of claim 1 , wherein the n-type work function metal layer is an aluminum-containing layer and has formula as MAIX, wherein M is Hf, Ti, Ta, Zr, or Nb, and X is C or Si.
9. A method, comprising:
forming a semiconductor fin over a substrate;
forming a dummy gate structure over the semiconductor fin;
forming source and drain regions in the semiconductor fin and on opposite sides of the dummy gate structure;
removing the dummy gate structure to expose the semiconductor fin;
forming a gate dielectric layer over the semiconductor fin;
forming a first work function metal layer over and in contact with the gate dielectric layer;
forming a second work function metal layer over the first work function metal layer; and
forming a gate electrode over the second work function metal layer, wherein from a first interface between the first work function metal layer and the second work function metal layer toward a second interface between the second work function metal layer and the gate electrode, a concentration of a work function material in the work function metal layer increases from a first non-zero value to a peak value, and then decreases from the peak value to a second non-zero value, and wherein the first and second non-zero values are lower than about 35%.
10. The method of claim 9 , wherein forming the gate dielectric layer comprises forming a high-k dielectric cap over the semiconductor fin, wherein the first work function metal layer is in contact with the high-k dielectric cap.
11. The method of claim 10 , wherein forming the gate dielectric layer comprises forming a high-k dielectric layer over the semiconductor fin prior to forming the high-k dielectric cap.
12. The method of claim 9 , wherein the second work function metal layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
13. The method of claim 9 , wherein the first work function metal layer has a vacuum work function value greater than about 4.4 eV, and the second work function metal layer has a vacuum work function value smaller than about 4.4 eV.
14. The method of claim 9 , wherein the second work function metal layer is an aluminum-containing layer and has formula as MAIX, wherein M is Hf, Ti, Ta, Zr, or Nb, and X is C or Si.
15. The method of claim 9 , wherein the work function material comprises aluminum.
16. A method, comprising:
forming a semiconductor fin over a substrate;
forming a dummy gate structure over the semiconductor fin;
forming source and drain regions in the semiconductor fin and on opposite sides of the dummy gate structure;
removing the dummy gate structure to expose the semiconductor fin;
forming a metal layer over the semiconductor fin;
forming a work function metal layer over the metal layer; and
forming a gate electrode over the work function metal layer, wherein from a first interface between the metal layer and the work function metal layer toward a second interface between the work function metal layer and the gate electrode, an aluminum concentration in the work function metal layer increases from a first non-zero value to a peak value, and then decreases from the peak value to a second non-zero value, and wherein the first and second non-zero values are lower than about 35%.
17. The method of claim 16 , wherein the work function metal layer is formed at a temperature in a range from about 350° C. to about 500° C.
18. The method of claim 17 , wherein the gate electrode is formed at a temperature in a range from about 250° C. to about 550° C.
19. The method of claim 16 , wherein a thickness of the work function metal layer is in a range from about 25 Å to about 30 Å.
20. The method of claim 16 , further comprising:
forming a liner lining a lower portion of a sidewall of the semiconductor fin;
forming an isolation structure over the liner;
forming an interfacial layer lining an upper portion of the sidewall of the semiconductor fin and in contact with the liner; and
forming a high-k dielectric layer over the interfacial layer and in contact with the isolation structure.