Semiconductor structure and method for manufacturing thereof
View Patent ↗A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.
1. A method for manufacturing a semiconductor structure, comprising:
forming an isolation stack over a substrate having a conductive region and an isolation region at a first surface of the substrate, and having a conductive region contact and a gate structure over the conductive region and the isolation region, respectively, wherein the gate structure is laterally surrounded by a spacer;
forming a first recess traversing the isolation stack over the gate structure;
forming a second recess traversing the isolation stack over the conductive region contact;
forming a recap layer over the isolation stack, the first recess and the second recess;
removing a bottom portion of the recap layer in the first recess and the second recess, and thereby a top surface of the gate structure is exposed from the recap layer; and
forming a first via contact and a second via contact in the first recess and the second recess, respectively.
2. The method of claim 1 ,
wherein the removing the bottom portion of the recap layer in the first recess and the second recess provides a top surface of the spacer exposed from the recap layer.
3. The method of claim 1 , wherein the gate structure and the conductive region contact are free from exposed after forming the first recess and the second recess.
4. The method of claim 1 , wherein forming the isolation stack includes forming a first etch stop layer over the gate structure.
5. The method of claim 4 , wherein the forming the first recess etches the isolation stack to expose a bottom surface of the first recess defined by the first etch stop layer.
6. The method of claim 5 , wherein the forming the isolation stack includes forming a second etch stop layer over the first etch stop layer, and
wherein the forming the second recess etches the isolation stack to expose a bottom surface of the second recess defined by the second etch stop layer.
7. The method of claim 5 , wherein the forming the recap layer over the first recess includes depositing the recap layer on the bottom surface of the first recess before the removing.
8. The method of claim 7 , wherein the removing the bottom portion of the recap layer includes etching the recap layer from the bottom surface of the first recess and a lower portion of sidewalls of the first recess.
9. The method of claim 1 , wherein forming the first via contact includes depositing a conductive material directly interfacing the recap layer.
10. The method of claim 1 , further comprising:
forming the conductive region in substrate by growing an epitaxial region.
11. A method for manufacturing a semiconductor structure, comprising:
providing a substrate having an epitaxial region and an isolation region;
forming a gate structure extending over the isolation region and adjacent the epitaxial region;
depositing a plurality of dielectric layers over the epitaxial region and the gate structure;
etching a first recess extending through the plurality of dielectric layers to a first layer of the plurality of dielectric layers, wherein a bottom surface of the first recess is defined by the first layer;
forming a second recess extending through the plurality of dielectric layers to a second layer of the plurality of dielectric layers, wherein a bottom surface of the second recess is defined by the second layer, and wherein the second layer is disposed over the first layer;
forming a recap layer along sidewalls and the bottom surface of the first recess and along sidewalls and the bottom surface of the second recess;
removing the recap layer from a bottom region of the sidewalls and the bottom surface of the first recess and a bottom region of the sidewalls and the bottom surface of the second recess; and
forming a first via contact and a second via contact in the first recess and the second recess, respectively.
12. The method of claim 11 , wherein the forming the first via contact includes extending the first recess to the gate structure.
13. The method of claim 11 , wherein the forming the second via contact includes extending the second recess to a conductive region contact extending above the epitaxial region.
14. The method of claim 11 , wherein after the removing the recap layer from the bottom region of the sidewalls and the bottom surface of the first recess, the recap layer is disposed on a center region of the sidewalls of the first recess.
15. The method of claim 11 , wherein the forming the gate structure includes depositing a spacer abutting the gate structure.
16. The method of claim 15 , further comprising:
after the removing the recap layer, extending the first recess to expose a top surface of the spacer and the gate structure.
17. A method for manufacturing a semiconductor structure, comprising:
forming a gate structure over a substrate;
depositing a plurality of dielectric layers over the gate structure;
forming a recess extending through the plurality of dielectric layers to provide a bottom surface of the recess defined by a first etch stop layer of the plurality of dielectric layers;
conformally depositing a recap layer along sidewalls and the bottom surface of the recess;
performing an etching process, wherein the etching process removes the recap layer from a bottom region of the sidewalls and the bottom surface of the recess and extends the recess to expose a top surface of the gate structure; and
filling the extended recess with conductive material.
18. The method of claim 17 , wherein the etching process is an anisotropic etching process.
19. The method of claim 17 , wherein the extending the recess exposes a spacer of the gate structure.
20. The method of claim 19 , wherein the extending the recess exposes a second etch stop layer disposed over the spacer.