Semiconductor structure and method for manufacturing semiconductor structure
A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate, a trench and a word line. The substrate includes an isolation structure and an active area. The active area includes irons of a first type. The trench is arranged in the active area, an inner surface of the trench includes an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the inversion doping layer is arranged above the oxide layer. The word line is arranged in the trench. The inversion doping layer includes ions of a second type. The first type is contrary to the second type.
1. A semiconductor structure, comprising:
a substrate comprising an isolation structure and an active region, the active region comprising ions of a first type;
a trench arranged in the active region, an inner surface of the trench comprising an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the oxide layer being arranged between the inversion doping layer and the active region; and
a word line arranged in the trench,
wherein the inversion doping layer comprises ions of a second type, and the first type is contrary to the second type; and
wherein the inner surface of the trench further comprises:
a protective layer in contact with the inversion doping layer, the inversion doping layer being sandwiched between a bottom end of the protective layer and a top end of the oxide layer.
2. The semiconductor structure of claim 1 , wherein the inversion doping layer comprises:
a side wall section in contact with the protective layer; and
a bottom wall section sandwiched between the bottom end of the protective layer and the top end of the oxide layer, the bottom wall section being perpendicular to the side wall section,
wherein the protective layer, the bottom wall section and the oxide layer form the inner surface of the trench.
3. The semiconductor structure of claim 2 , wherein each of the bottom end of the protective layer and the top end of the oxide layer is in contact with the bottom wall section.
4. The semiconductor structure of claim 1 , wherein the word line comprises:
a barrier layer arranged on a surface of the oxide layer, and
a conductive layer arranged on a surface of the barrier layer.
5. The semiconductor structure of claim 2 , wherein the word line comprises:
a barrier layer arranged on a surface of the oxide layer, and
a conductive layer arranged on a surface of the barrier layer.
6. The semiconductor structure of claim 3 , wherein the word line comprises:
a barrier layer arranged on a surface of the oxide layer, and
a conductive layer arranged on a surface of the barrier layer.
7. The semiconductor structure of claim 4 , wherein a top end of the barrier layer is flush with a top end of the conductive layer.
8. A semiconductor structure, comprising:
a substrate comprising an isolation structure and an active region, the active region comprising ions of a first type;
a trench arranged in the active region, an inner surface of the trench comprising an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the inversion doping layer being arranged above the oxide layer; and
a word line arranged in the trench,
wherein the inversion doping layer comprises ions of a second type, and the first type is contrary to the second type;
wherein the inner surface of the trench further comprises:
a protective layer in contact with the inversion doping layer, the inversion doping layer being sandwiched between a bottom end of the protective layer and a top end of the oxide layer;
wherein the word line comprises:
a barrier layer arranged on a surface of the oxide layer, and
a conductive layer arranged on a surface of the barrier layer; and
the semiconductor structure further comprising:
an insulation layer arranged above the barrier layer and the conductive layer, each of a top end of the barrier layer and a top end of the conductive layer being in contact with a bottom end of the insulation layer,
wherein the barrier layer covers a side wall and a bottom wall of the oxide layer, and a plane where the top end of the barrier layer is located is lower than a plane where the bottom end of the protective layer is located.
9. The semiconductor structure of claim 8 , wherein the plane where the top end of the barrier layer is located is 10 nm to 20 nm lower than the plane where the bottom end of the protective layer is located.