Failover methods and systems in three-dimensional memory device
Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.
1. A memory device comprising:
a base memory die having:
a bottom base-die face including a bottom base-die primary data contact;
a top base-die face extending through the three-dimensional memory device and including a top base-die primary data contact and a top base-die secondary data contact;
a switchable connection between the bottom base-die primary data contact and the top base-die primary data contact;
base-die drive circuitry having a drive-circuitry input coupled to the top base-die secondary data contact and a drive-circuitry output coupled to the bottom base-die primary data contact; and
a base-die memory core coupled to the drive-circuitry input; and
an alternate memory die affixed atop the base memory die, the alternate memory die having:
a bottom alternate-die face extending through the three-dimensional memory device adjacent the top base-die face, the bottom alternate-die face including a bottom alternate-die primary data contact in contact with the top base-die primary data contact and a bottom alternate-die secondary data contact in contact with the top base-die secondary data contact; and
an alternate-die memory core coupled to the drive-circuitry input via the bottom alternate-die secondary data contact and the top base-die secondary data contact.
2. The memory device of claim 1 , the base-die drive circuitry including a serializer coupled between the top base-die secondary data contact and the bottom base-die primary data contact.
3. The memory device of claim 2 , the base-die drive circuitry including an enable terminal to receive an enable signal, the base-drive circuitry exhibiting a first output capacitance when the enable signal asserted and a lower second output capacitance when the enable signal is deasserted.
4. The memory device of claim 1 , the base memory die including second base-die drive circuitry having a second drive-circuitry output coupled to the top base-die secondary data contact and a second drive-circuitry input coupled to the bottom base-die primary data contact.
5. The memory device of claim 4 , the second base-die drive circuitry including a deserializer coupled between the bottom base-die primary data contact and the top base-die secondary data contact.
6. The memory device of claim 1 , wherein at least one of the base-die memory core and the alternate-die memory core comprises dynamic, random-access memory.
7. The memory device of claim 1 , further comprising a register to close the switchable connection between the bottom base-die primary data contact and the top base-die primary data contact to connect the bottom alternate-die primary data contact to the bottom base-die primary data contact.
8. The memory device of claim 1 , further comprising a data-buffer integrated circuit affixed to the bottom base-die face, the data-buffer integrated circuit to communicate read data from the bottom base-die primary data contact.
9. The memory device of claim 1 , the alternate memory die including a top alternate-die face having a top alternate-die primary data contact and a second switchable connection between the bottom alternate-die primary data contact and the top alternate-die primary data contact.
10. The memory device of claim 9 , the alternate memory die including alternate-die drive circuitry having an alternate-die drive-circuitry input coupled to alternate-die memory core and an alternate-die drive-circuitry output coupled to the bottom alternate-die primary data contact.
11. The memory device of claim 1 , the base memory die further including an enable node coupled to the base-die drive circuitry, the enable node to enable the base-die drive circuitry responsive to an enable signal.
12. The memory device of claim 11 , wherein the enable signal opens the switchable connection.
13. A memory module comprising:
a printed-circuit board;
a base memory die including:
a bottom base-die face including a bottom base-die primary data contact electrically connected to the printed-circuit board;
a top base-die face including a top base-die primary data contact and a top base-die secondary data contact;
a switchable connection between the bottom base-die primary data contact and the top base-die primary data contact;
base-die drive circuitry having a drive-circuitry input coupled to the top base-die secondary data contact and a drive-circuitry output coupled to the bottom base-die primary data contact; and
a base-die memory core coupled to the drive-circuitry input; and
an alternate memory die affixed atop the base memory die, the alternate memory die including:
a bottom alternate-die face adjacent the top base-die face, the bottom alternate-die face including a bottom alternate-die primary data contact in contact with the top base-die primary data contact and a bottom alternate-die secondary data contact in contact with the top base-die secondary data contact; and
an alternate-die memory core coupled to the drive-circuitry input via the bottom alternate-die secondary data contact and the top base-die secondary data contact.
14. The memory module of claim 13 , the base-die drive circuitry including a serializer coupled between the top base-die secondary data contact and the bottom base-die primary data contact.
15. The memory module of claim 14 , the base-die drive circuitry including an enable terminal to receive an enable signal, the base-drive circuitry exhibiting a first output capacitance when the enable signal asserted and a lower second output capacitance when the enable signal is deasserted.
16. The memory module of claim 13 , the base memory die including second base-die drive circuitry having a second drive-circuitry output coupled the top base-die secondary data contact and a second drive-circuitry input coupled to the bottom base-die primary data contact.
17. The memory module of claim 16 , the second base-die drive circuitry including a deserializer coupled between the bottom base-die primary data contact and the top base-die secondary data contact.
18. The memory module of claim 13 , wherein at least one of the base-die memory core and the alternate-die memory core comprises dynamic random-access memory.
19. The memory module of claim 13 , further comprising a register to close the switchable connection between the bottom base-die primary data contact and the top base-die primary data contact to connect the bottom alternate-die primary data contact to the bottom base-die primary data contact.