Method of manufacturing a trench capacitor with wafer bow
A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.
1. A deep trench capacitor, comprising:
a first deep trench and a second deep trench disposed in a substrate;
a first dielectric layer, a first conductive layer, and a second dielectric layer disposed on the first deep trench and the second deep trench, respectively;
a first upper electrode disposed on the second dielectric layer in the first deep trench;
a second upper electrode disposed on the second dielectric layer in the second deep trench and spaced apart from the first upper electrode;
a first gap-fill insulating film disposed on the first upper electrode, wherein a first void is formed in the first deep trench;
a second gap-fill insulating film disposed on the second upper electrode and spaced apart from the first gap-fill insulating film, wherein a second void is formed in the second deep trench;
a first inter-layer insulating film disposed on the first gap-fill insulating film and the second gap-fill insulating film;
first level metal interconnects disposed on the first inter-layer insulating film;
a second inter-layer insulating film disposed on the first inter-layer insulating film; and
second level metal interconnects disposed on the second inter-layer insulating film.
2. The deep trench capacitor of claim 1 , wherein a side surface of the first upper electrode is aligned with a side surface of the first gap-fill insulating film, and
wherein a side surface of the second upper electrode is aligned with a side surface of the second gap-fill insulating film.
3. The deep trench capacitor of claim 1 , further comprising:
a second conductive layer disposed on the second dielectric layer;
a first upper dielectric layer disposed between the second conductive layer and the first upper electrode disposed on the first deep trench; and
a second upper dielectric layer disposed between the second conductive layer and the second upper electrode disposed on the second deep trench, wherein the second upper dielectric layer is spaced apart from the first upper dielectric layer.
4. The deep trench capacitor of claim 1 , wherein one of the first level metal interconnects contacts the first upper electrode and overlaps the first void formed in the first deep trench, and
wherein the other of the first level metal interconnects contacts the first conductive layer.
5. The deep trench capacitor of claim 1 , wherein a portion of the first void is disposed above a top surface of the substrate.
6. The deep trench capacitor of claim 1 , further comprising:
a doping region disposed below the first void and the second void, the doping region disposed in the substrate,
wherein each side surface of the first upper electrode and the second upper electrode contacts the first inter-layer insulating film.
7. The deep trench capacitor of claim 3 , wherein the first upper electrode has a thickness greater than a thickness of the first conductive layer or the second conductive layer,
wherein the first dielectric layer and the second dielectric layer comprise a first oxide layer, a nitride layer, and a second oxide layer, respectively, and
wherein the first conductive layer, the second conductive layer, the first upper electrode, and the second upper electrode comprise a poly-silicon material.
8. A deep trench capacitor, comprising:
a first deep trench and a second deep trench disposed in a substrate;
a first dielectric layer, a first conductive layer, and a second dielectric layer, disposed on the first and second deep trenches, respectively;
a first upper electrode and a second upper electrode disposed on the second dielectric layer and disposed on the first and second deep trenches, respectively;
a first gap-fill insulating film and a second gap-fill insulating film spaced apart from each other and disposed on the first and second deep trenches, respectively, wherein a first void and a second void are formed in the first gap-fill insulating film and the second gap-fill insulating film, respectively;
a first inter-layer insulating film disposed on the first gap-fill insulating film and the second gap-fill insulating film; and
first level metal interconnects disposed on the first inter-layer insulating film.
9. The deep trench capacitor of claim 8 , wherein a side surface of the first upper electrode is aligned with a side surface of the first gap-fill insulating film, and
wherein a side surface of the second upper electrode is aligned with a side surface of the second gap-fill insulating film.
10. The deep trench capacitor of claim 8 , further comprising:
a second conductive layer disposed on the second dielectric layer;
a first upper dielectric layer disposed between the second conductive layer and the first upper electrode disposed on the first deep trench; and
a second upper dielectric layer disposed between the second conductive layer and the second upper electrode disposed on the second deep trench, wherein the second upper dielectric layer is spaced apart from the first upper dielectric layer.
11. The deep trench capacitor of claim 8 , wherein one of the first level metal interconnects contacts the first upper electrode and overlaps the first void formed in the first deep trench, and
wherein the other of the first level metal interconnects contacts the first conductive layer.