IP Library › Granted Patent US 12,288,810
Granted Patent B2
US 12,288,810 · App. 18/415,251 · Granted Apr 29, 2025

Backside contact structures and fabrication for metal on both sides of devices

Inventors: Patrick Morrow (Portland, OR); Rishabh Mehandru (Portland, OR); Aaron D. Lilak (Beaverton, OR); Kimin Jun (Hillsboro, OR)
Assignee: Intel Corporation
H01L29/41791H01L21/823431H01L27/1266H01L29/0847H01L29/401H01L29/4236H01L29/6653H01L29/66553H01L29/66795H01L29/66803H01L29/78H01L29/785H01L21/2254H01L21/26513H01L29/66545
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Quick Facts
Patent No.
US 12,288,810
App. No.
18/415,251
Granted
Apr 29, 2025
Kind
B2
Abstract

An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

Claims (49)

1. A method of fabricating an integrated circuit structure, the method comprising:

forming a semiconductor body having a top, a bottom, a first side and a second side, the first side and the second side between the top and the bottom, and the first side opposite the second side;

forming a gate structure at least over the top and extending along the first side and the second side of the semiconductor body;

forming a first source or drain structure at a first side of the gate structure;

forming a second source or drain structure at a second side of the gate structure, the second side opposite the first side; and

forming a conductive contact vertically below and in contact with the first source or drain structure.

2. The method of claim 1 , wherein the conductive contact is further along a first side of the first source or drain structure.

3. The method of claim 2 , wherein the conductive contact is further along a second side of the first source or drain structure.

4. The method of claim 1 , wherein the gate structure extends along only a portion of the first side and the second side of the semiconductor body.

5. The method of claim 1 , further comprising:

forming a second conductive contact vertically above and in contact with the second source or drain structure.

6. The method of claim 5 , further comprising:

forming an epitaxial semiconductor structure vertically between the second conductive contact and the second source or drain structure.

7. The method of claim 1 , further comprising:

forming a second conductive contact vertically above and in contact with the first source or drain structure.

8. The method of claim 1 , further comprising:

forming a second conductive contact vertically below and in contact with the second source or drain structure.

9. The method of claim 1 , further comprising:

forming a second conductive contact vertically above and in contact with the first source or drain structure; and

forming a third conductive contact vertically below and in contact with the second source or drain structure.

10. A method of fabricating an integrated circuit structure, the method comprising:

forming a semiconductor body having a top, a bottom, a first side and a second side, the first side and the second side between the top and the bottom, and the first side opposite the second side;

forming a gate structure over the top and extending along the first side and the second side of the semiconductor body;

forming a first source or drain structure in the semiconductor body at a first side of the gate structure;

forming a second source or drain structure in the semiconductor body at a second side of the gate structure, the second side opposite the first side; and

forming a conductive contact on the bottom of the semiconductor body at a location vertically beneath the first source or drain structure.

11. The method of claim 10 , wherein the conductive contact is further along a portion of the first side of the semiconductor body.

12. The method of claim 11 , wherein the conductive contact is further along a portion of the second side of the semiconductor body.

13. The method of claim 10 , wherein the gate structure extends along only a portion of the first side and the second side of the semiconductor body.

14. The method of claim 10 , further comprising:

forming a second conductive contact over the top of the semiconductor body at a location vertically above the second source or drain structure.

15. The method of claim 14 , further comprising:

forming an epitaxial semiconductor structure vertically between the second conductive contact and the top of the semiconductor body.

16. The method of claim 10 , further comprising:

forming a second conductive contact over the top of the semiconductor body at a location vertically above the first source or drain structure.

17. The method of claim 10 , further comprising:

forming a second conductive contact on the bottom of the semiconductor body at a location vertically below the second source or drain structure.

18. The method of claim 10 , further comprising:

forming an epitaxial semiconductor structure on the top of the semiconductor body at the first side of the gate structure.

19. A method of fabricating a computing device, the method comprising:

providing a board; and

coupling an integrated circuit die to the board, the integrated circuit die comprising an integrated circuit structure, the integrated circuit structure comprising:

a semiconductor body having a top, a bottom, a first side and a second side, the first side and the second side between the top and the bottom, and the first side opposite the second side;

a gate structure at least over the top and extending along the first side and the second side of the semiconductor body;

a first source or drain structure at a first side of the gate structure;

a second source or drain structure at a second side of the gate structure, the second side opposite the first side; and

a conductive contact vertically below and in contact with the first source or drain structure.

20. The method of claim 19 , further comprising:

coupling a memory to the board.

Continuity (5)
Continuation 18131336 · Apr 5, 2023
Continuation 17522764 · Nov 9, 2021
Continuation 16999508 · Aug 21, 2020
Division 15747119
Related Publication 20240154011A1 · May 9, 2024
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