Lateral diffusion metal oxide semiconductor device and method for fabricating the same
A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.
1. A lateral diffusion metal oxide semiconductor (LDMOS) device, comprising:
a first fin-shaped structure on a substrate;
a shallow trench isolation (STI) adjacent to the first fin-shaped structure;
a first gate structure on the first fin-shaped structure;
a spacer adjacent to the first gate structure, wherein a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure;
a contact field plate adjacent to the first gate structure and directly on the STI; and
an interlayer dielectric (ILD) layer between the spacer and the contact field plate, wherein a bottom surface of the ILD layer is even with a bottom surface of the contact field plate and lower than a bottom surface of the first gate structure.
2. The semiconductor device of claim 1 , further comprising:
a second fin-shaped structure adjacent to the first fin-shaped structure, wherein the STI is between the first fin-shaped structure and the second fin-shaped structure;
a second gate structure on the second fin-shaped structure;
a source region adjacent to one side of the first gate structure on the first fin-shaped structure;
a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;
the interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; and
a first contact plug on the source region and a second contact plug on the drain region.
3. The semiconductor device of claim 2 , wherein the contact field plate is between the first gate structure and the second gate structure.
4. The semiconductor device of claim 2 , wherein a width of the second gate structure is less than a width of the first gate structure.
5. The semiconductor device of claim 2 , wherein the contact field plate and the first contact plug comprise same material.
6. The semiconductor device of claim 2 , wherein a bottom surface of the contact field plate is lower than a bottom surface of the first contact plug.
7. The semiconductor device of claim 2 , wherein top surfaces of the contact field plate and the first contact plug are coplanar.
8. A lateral diffusion metal oxide semiconductor (LDMOS) device, comprising:
a first fin-shaped structure on a substrate;
a shallow trench isolation (STI) adjacent to the first fin-shaped structure;
a first gate structure on the first fin-shaped structure and the STI, wherein a bottom surface of the first gate structure comprises a step-shape;
a first spacer adjacent to one side of the first gate structure;
a second spacer adjacent to another side of the first gate structure; and
a contact field plate adjacent to the first gate structure and directly on the STI, wherein a bottom surface of the second spacer is lower than a bottom surface of the first spacer and even with the bottom surface of the first gate structure and a bottom surface of the contact field plate.
9. The semiconductor device of claim 8 , further comprising:
a second fin-shaped structure adjacent to the first fin-shaped structure, wherein the STI is between the first fin-shaped structure and the second fin-shaped structure;
a second gate structure on the second fin-shaped structure;
a source region adjacent to one side of the first gate structure on the first fin-shaped structure;
a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;
an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; and
a first contact plug on the source region and a second contact plug on the drain region.
10. The semiconductor device of claim 9 , wherein the contact field plate is between the first gate structure and the second gate structure.
11. The semiconductor device of claim 9 , wherein the contact field plate and the first contact plug comprise same material.
12. The semiconductor device of claim 9 , wherein a bottom surface of the contact field plate is lower than a bottom surface of the first contact plug.
13. The semiconductor device of claim 9 , wherein top surfaces of the contact field plate and the first contact plug are coplanar.