Power adjustment method of upper electrode power supply and semiconductor process apparatus
The present disclosure provides a power adjustment method of an upper electrode power supply of a semiconductor process apparatus. The method includes obtaining a processing load of an upper electrode power supply of a reference process chamber and a processing load of an upper electrode power supply of a current process chamber corresponding to semiconductor process step, when starting to perform a semiconductor process step, determining a power compensation coefficient for the current process chamber relative to the reference process chamber based on the processing load of the current process chamber and the processing load the reference process chamber, and controlling the upper electrode power supply to output compensation power. The compensation power is a product of the set power of the upper electrode power supply of the current process chamber corresponding to the semiconductor process step and the corresponding power compensation coefficient.
1. A power adjustment method of an upper electrode power supply of a semiconductor process apparatus, comprising:
obtaining a processing load of an upper electrode power supply of a reference process chamber and a processing load of an upper electrode power supply of a current process chamber corresponding to a semiconductor process step;
when starting the semiconductor process step, determining a power compensation coefficient corresponding to the semiconductor process step for the current process chamber relative to the reference process chamber according to the processing load of the current process chamber and the processing load of the reference process chamber, the processing load of the current process chamber being a sum of a circuit load of the current process chamber and a plasma load corresponding to the semiconductor process step, the processing load of the reference process chamber being a sum of a circuit load of the reference process chamber and the plasma load of the semiconductor processes; and
controlling the upper electrode power supply of the current process chamber to output a compensation power during the semiconductor process steps, the compensation power being a product of a set power of the upper electrode power supply of the current process chamber corresponding to the semiconductor process step and the corresponding power compensation coefficient.
2. The power adjustment method according to claim 1 , wherein the compensation coefficient is a ratio between the processing load of the current process chamber and the processing load of the reference process chamber.
3. The power adjustment method according to claim 1 , wherein:
upper electrode circuits are arranged at the reference process chamber and the current process chamber;
the upper electrode power supply is configured to output power to a corresponding process chamber through a corresponding upper electrode circuit; and
obtaining the processing load of the upper electrode power supply of the reference process chamber and the processing load of the upper electrode power supply of the current process chamber corresponding to the semiconductor process step includes:
obtaining the plasma load corresponding to the semiconductor process step;
adding the circuit load of the reference process chamber and the plasma load of the semiconductor processes to obtain the processing load of the reference process chamber performing the semiconductor processes; and
adding the circuit load of the current process chamber and the plasma load of the performed semiconductor processes to obtain the processing load of the current process chamber performing the corresponding semiconductor processes.
4. The power adjustment method according to claim 3 , wherein obtaining the plasma load corresponding to the semiconductor process step includes:
when performing the semiconductor process step, controlling the upper electrode power supply of the reference process chamber to output a processing power and detecting a process current between the upper electrode power supply and the reference process chamber;
obtaining the processing load of the reference process chamber according to the processing power and the process current; and
subtracting the circuit load of the reference process chamber from the processing load of the reference process chamber to obtain the plasma load corresponding to the semiconductor process step.
5. The power adjustment method according to claim 4 , wherein the processing load is a ratio of the processing power to square of the process current.
6. The power adjustment method according to claim 3 , wherein obtaining the circuit load of any one of the reference process chamber and the current process chamber includes:
controlling the upper electrode power supply of the process chamber to output detection power to detect a detection current between the upper electrode power supply and the process chamber, the plasma being not ignited in the process chamber under the detection power; and
obtaining the circuit load of the process chamber according to the detection power and detection current of the process chamber.
7. The power adjustment method according to claim 6 , wherein the circuit load is a ratio of the detection power to square of the detection current.
8. A semiconductor process apparatus comprising:
a plurality of process chambers, the semiconductor process apparatus being configured to adjust power of upper electrode power supplies of the plurality of process chambers, any one process chamber of the plurality of process chambers being used as a reference process chamber, a process chamber of the other process chambers that performs a semiconductor process step being a current process chamber;
an acquisition unit configured to obtain a processing load of an upper electrode power supply of the reference process chamber and a processing load of an upper electrode power supply of the current process chamber corresponding to the semiconductor process step;
a calculation unit configured to, when starting the semiconductor process step, determine a power compensation coefficient corresponding to the semiconductor process step for the current process chamber relative to the reference process chamber according to the processing load of the current process chamber and the processing load of the reference process chamber, the processing load of the current chamber being a sum of a circuit load of the current process chamber and a plasma load corresponding to the semiconductor process step, the processing load of the reference process chamber being a sum of a circuit load of the reference process chamber and the plasma load of the semiconductor processes; and
a control unit configured, when performing the semiconductor process step to control the upper electrode power supply of the current process chamber to output a compensation power, the compensation power being a product of a set power of the upper electrode power supply of the current process chamber corresponding to the semiconductor process step and the corresponding power compensation coefficient.
9. The semiconductor process apparatus according to claim 8 , further comprising:
the plurality of process chambers, one process chamber being able to be used as the reference process chamber, the power of the upper electrode supply of other process chambers being adjusted through the power adjustment method.
10. The semiconductor process apparatus according to claim 8 , further comprising:
a plurality of current detection devices, a number of the plurality of current detection devices being same as a number of the process chambers, and the current detection devices being arranged between the electrode power supplies and the corresponding process chambers in a one-to-one correspondence, the current detection devices being configured to obtain a process current and/or a detection current between the corresponding upper electrode power supplies and the corresponding process chambers, and the detection current referring to a current outputted by the upper electrode power supply when the plasma is not ignited in the process chamber.
11. The power adjustment method according to claim 4 , further comprising:
storing the plasma load corresponding to the semiconductor process step in a data structure for later access.
12. The power adjustment method according to claim 11 , wherein the data structure comprises a respective plasma load value corresponding to each of a plurality of semiconductor process steps including the semiconductor process step.