Self-aligned buried power rail cap for semiconductor devices
A buried power rail is provided in a non-active device region. The buried power rail includes a dielectric liner located on a lower portion of a sidewall and a bottommost surface of the buried power rail. A dielectric cap is located on an upper portion of the sidewall of the buried power rail as well as on a topmost surface of the buried power rail. The dielectric cap is present during the fabrication of a functional gate structure and thus the problems associated with prior art buried power rails are circumvented. The dielectric cap can be removed after the functional gate structure has been formed and a via to buried power rail (VBPR) contact structure can be formed in contact with the buried power rail. In some applications, and after a gate cut process, a gate cut dielectric structure can be formed in contact with the dielectric cap.
1. A method of forming a semiconductor device, the method comprising:
forming a buried power rail opening that extends entirely through a shallow trench isolation layer and partially through a semiconductor substrate;
forming a dielectric material layer and a power rail conductive material in the buried power rail opening;
recessing the power rail conductive material to provide a buried power rail located at a bottom portion of the buried power rail opening;
recessing the dielectric material layer to provide a dielectric material liner that is located on a lower portion of a sidewall of the buried power rail and on a bottommost surface of the buried power rail; and
forming a dielectric cap on an upper portion of the sidewall of the buried power rail and on a topmost surface of the buried power rail.
2. The method of claim 1 , wherein the buried power rail opening is formed in a non-active device region.
3. The method of claim 2 , further comprising forming a source/drain region of a functional gate structure located in an active device region, wherein the active device region is located laterally adjacent to the non-active device region.
4. The method of claim 3 , wherein the source/drain region of the functional gate structure is located on a buried dielectric insulator layer.
5. The method of claim 3 , further comprising forming a source/drain contact structure contacting a surface of the source/drain region of the functional gate structure.
6. The method of claim 3 , further comprising forming an interlayer dielectric material layer that embeds the source/drain contact structure, the source/drain region, and an upper portion of the dielectric cap.
7. The method of claim 3 , wherein the functional gate structure is wrapped around a plurality of vertically stacked and spaced apart semiconductor channel material nano sheets.
8. The method of claim 2 , further comprising
forming a functional gate structure in an active device region, wherein the active device region is located laterally adjacent to the non-active device region;
forming an interlayer dielectric material layer; and
replacing the dielectric cap with a via to buried power rail (VBPR) contact structure, wherein the VBPR contact structure is formed in contact with the buried power rail.
9. The method of claim 8 , wherein the replacing the dielectric cap comprises forming an VBPR contact opening in the interlayer dielectric material layer that physically exposes the dielectric cap, and performing an etching process that is selective in removing the dielectric cap.
10. The method of claim 9 , wherein the etching process forms an undercut region beneath a portion of the interlayer dielectric material layer.
11. The method of claim 9 , wherein the VBPR contact structure includes a bottom portion that is located in, and beneath, the undercut region.
12. The method of claim 11 , wherein the VBPR contact structure contacts an upper portion of the sidewall of the buried power rail and the topmost surface of the buried power rail.
13. The method of claim 9 , further comprising forming source/drain contact openings in the interlayer dielectric material, wherein at least one of the source/drain contact openings merges with the VBPR contact opening forming a merged contact opening, wherein the VBPR contact structure is formed in the merged contact opening.
14. The method of claim 1 , wherein the dielectric cap has a topmost surface that is higher than a topmost surface of the semiconductor substrate, or higher than a topmost surface of the shallow trench isolation structure.
15. The method of claim 1 , wherein the dielectric liner has an upper portion contained in the shallow trench isolation structure and a lower portion contained in the semiconductor substrate.
16. The method of claim 1 , further comprising forming an interlayer dielectric material layer, wherein the interlayer dielectric material layer embeds an upper portion of the dielectric cap.
17. The method of claim 1 , wherein the dielectric cap is wider than an entirety of the buried power rail.
18. The method of claim 1 , wherein the dielectric cap is composed of a compositionally different dielectric material than a dielectric material that provides the dielectric material liner.
19. The method of claim 1 , further comprising forming a gate cut dielectric structure on a surface of the dielectric cap.