Method of manufacturing a semiconductor memory device with a low voltage transistor
According to one embodiment, a semiconductor device includes: a first well region of N-type and a second well region of P-type; a PMOS transistor provided in the first well region; and an NMOS transistor provided in the second well region. The PMOS transistor includes a first gate insulating layer and a first gate electrode. The NMOS transistor includes a second gate insulating layer and a second gate electrode. The first gate electrode includes a first semiconductor layer of P-type, a first insulating layer, and a first conductive layer. The second gate electrode includes a second semiconductor layer of N-type, a second insulating layer, and a second conductive layer. A film thickness of the first insulating layer is thicker than a film thickness of the second insulating layer.
1. A method for manufacturing a semiconductor device comprising:
forming a first well region of N-type and a second well region of P-type, the first well region and the second well region being provided in a surface region of a substrate;
forming an element isolation region between the first well region and the second well region; and
forming a PMOS transistor in the first well region and an NMOS transistor in the second well region, the PMOS transistor including a side wall, a first gate insulating layer provided on the first well region, and a first gate electrode provided on the first gate insulating layer, and the NMOS transistor including a second gate insulating layer provided on the second well region and a second gate electrode provided on the second gate insulating layer,
wherein
the first gate electrode includes:
a first semiconductor layer of P-type, a side surface of the first semiconductor layer being in contact with the side wall;
a first insulating layer provided on the first semiconductor layer, a side surface of the first insulating layer being in contact with the side wall;
a first conductive layer provided on the first insulating layer, a side surface of the first conductive layer being in contact with the side wall; and
a third semiconductor layer provided between the first gate insulating layer and the first semiconductor layer, the third semiconductor layer containing P-type semiconductor and carbon,
the second gate electrode includes:
a second semiconductor layer of N-type, a side surface of the second semiconductor layer being in contact with the side wall;
a second insulating layer provided on the second semiconductor layer; and
a second conductive layer provided on the second insulating layer, and
the forming the PMOS transistor and the NMOS transistor includes:
forming the first gate insulating layer on the first well region;
forming the second gate insulating layer on the second well region;
forming the first semiconductor layer of P-type on the first gate insulating layer;
forming the second semiconductor layer of N-type on the second gate insulating layer; and
forming the first insulating layer and the second insulating layer, a film thickness of the first insulating layer being thicker than a film thickness of the second insulating layer.
2. The method for manufacturing the semiconductor device according to claim 1 , wherein
the forming the first insulating layer and the second insulating layer includes:
forming a third insulating layer;
forming a mask on the third insulating layer in a PMOS transistor formation region;
removing a part of the third insulating layer in an NMOS transistor formation region;
removing the mask; and
forming the second insulating layer in the PMOS transistor formation region and the NMOS transistor formation region.
3. The method for manufacturing the semiconductor device according to claim 2 , wherein
the first insulating layer includes at least a part of the third insulating layer and a part of the second insulating layer.
4. The method for manufacturing the semiconductor device according to claim 1 , further comprising:
forming a first interconnect layer above the PMOS transistor and the NMOS transistor;
forming a plurality of second interconnect layers apart from each other above the first interconnect layer; and
forming a fifth semiconductor layer penetrating through the second interconnect layers and being contact with the first interconnect layer.
5. The method for manufacturing the semiconductor device according to claim 4 , further comprising:
forming a fifth insulating layer;
forming a charge storage layer on the fifth insulating layer; and
forming a sixth insulating layer on the charge storage layer.
6. The method for manufacturing the semiconductor device according to claim 5 , wherein
the fifth semiconductor layer is on the sixth insulating layer.
7. The method for manufacturing the semiconductor device according to claim 4 , wherein
the second gate electrode further includes a fourth semiconductor layer provided between the second semiconductor layer and the second insulating layer, the fourth semiconductor layer containing N-type semiconductor and carbon.
8. A method for manufacturing a semiconductor device comprising:
forming a first well region of N-type and a second well region of P-type, the first well region and the second well region being provided in a surface region of a substrate;
forming an element isolation region between the first well region and the second well region; and
forming a PMOS transistor in the first well region and an NMOS transistor in the second well region, the PMOS transistor including a side wall, a first gate insulating layer provided on the first well region, and a first gate electrode provided on the first gate insulating layer, and the NMOS transistor including a second gate insulating layer provided on the second well region and a second gate electrode provided on the second gate insulating layer,
wherein
the first gate electrode includes:
a first semiconductor layer of P-type, a side surface of the first semiconductor layer being in contact with the side wall;
a first insulating layer provided on the first semiconductor layer, a side surface of the first insulating layer being in contact with the side wall; and
a first conductive layer provided on the first insulating layer, a side surface of the first conductive layer being in contact with the side wall,
the second gate electrode includes:
a second semiconductor layer of N-type;
a second insulating layer provided on the second semiconductor layer; and
a second conductive layer provided on the second insulating layer,
the forming the PMOS transistor and the NMOS transistor includes:
forming the first gate insulating layer on the first well region;
forming the second gate insulating layer on the second well region;
forming the first semiconductor layer of P-type on the first gate insulating layer;
forming the second semiconductor layer of N-type on the second gate insulating layer; and
forming the first insulating layer and the second insulating layer, a film thickness of the first insulating layer being thicker than a film thickness of the second insulating layer, and
the forming the second semiconductor layer of N-type on the second gate insulating layer includes:
doping carbon into a surface region of the second semiconductor layer of N-type.
9. The method for manufacturing the semiconductor device according to claim 8 , wherein
the forming the first insulating layer and the second insulating layer includes:
forming the second insulating layer on the surface region of the second semiconductor layer of N-type.
10. A method for manufacturing a semiconductor device comprising:
forming a first well region of N-type and a second well region of P-type, the first well region and the second well region being provided in a surface region of a substrate;
forming an element isolation region between the first well region and the second well region; and
forming a PMOS transistor in the first well region and an NMOS transistor in the second well region, the PMOS transistor including a side wall, a first gate insulating layer provided on the first well region, and a first gate electrode provided on the first gate insulating layer, and the NMOS transistor including a second gate insulating layer provided on the second well region and a second gate electrode provided on the second gate insulating layer,
wherein
the first gate electrode includes:
a first semiconductor layer of P-type, a side surface of the first semiconductor layer being in contact with the side wall;
a first insulating layer provided on the first semiconductor layer, a side surface of the first insulating layer being in contact with the side wall; and
a first conductive layer provided on the first insulating layer, a side surface of the first conductive layer being in contact with the side wall,
the second gate electrode includes:
a second semiconductor layer of N-type;
a second insulating layer provided on the second semiconductor layer;
a second conductive layer provided on the second insulating layer; and
a fourth semiconductor layer provided between the second semiconductor layer and the second insulating layer, the fourth semiconductor layer containing N-type semiconductor and carbon, and
the forming the PMOS transistor and the NMOS transistor includes:
forming the first gate insulating layer on the first well region;
forming the second gate insulating layer on the second well region;
forming the first semiconductor layer of P-type on the first gate insulating layer;
forming the second semiconductor layer of N-type on the second gate insulating layer; and
forming the first insulating layer and the second insulating layer, a film thickness of the first insulating layer being thicker than a film thickness of the second insulating layer.