Integrated circuit structure and method with hybrid orientation for FinFET
The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
1. A method, comprising:
bonding a first semiconductor substrate and a second semiconductor substrate such that corresponding crystalline directions <001> have a 45-degree rotation;
forming a patterned mask on the second semiconductor substrate to cover a first region and expose a second region;
etching the second semiconductor substrate within the second region to expose the first semiconductor substrate in a trench;
forming a dielectric material layer on a sidewall of the second semiconductor substrate within the trench;
epitaxially growing a first semiconductor material layer over the first semiconductor substrate within the second region; and
patterning the second semiconductor substrate in the first region and the first semiconductor material layer in the second region to form a first fin in the first region and a second fin in the second region, wherein the first fin is oriented in a first direction and has a crystalline direction <100> along the first direction, wherein the second fin is oriented in the first direction and has a crystalline direction <110> along the first direction.
2. The method of claim 1 , wherein the bonding a first semiconductor substrate and a second semiconductor substrate includes bonding the first and second semiconductor substrates by a silicon oxide layer.
3. The method of claim 2 , wherein the etching the second semiconductor substrate within the second region includes further etching through the silicon oxide layer until the first semiconductor substrate is exposed within the second region.
4. The method of claim 3 , wherein the etching the second semiconductor substrate within the second region includes further recessing the first semiconductor substrate within the second region.
5. The method of claim 2 , further comprising epitaxially growing a second semiconductor material layer directly on the first semiconductor substrate within the second region.
6. The method of claim 5 , wherein
the epitaxially growing a first semiconductor material layer over the first semiconductor substrate within the second region includes epitaxially growing the first semiconductor material layer directly on the second semiconductor material layer; and
the second semiconductor material layer is different from the first semiconductor material layer in composition.
7. The method of claim 6 , wherein
the first and second semiconductor substrates are silicon substrates;
the epitaxially growing a first semiconductor material layer includes epitaxially growing a silicon germanium layer; and
the epitaxially growing a second semiconductor material layer includes epitaxially growing a silicon layer.
8. The method of claim 7 , wherein the epitaxially growing a second semiconductor material layer includes epitaxially growing the silicon layer such that a top surface of the silicon layer is coplanar with a top surface of the silicon oxide layer.
9. The method of claim 7 , further comprising performing a first polishing process to the second semiconductor substrate and the first semiconductor material layer to form a planarized top surface.
10. The method of claim 9 , wherein the patterning the second semiconductor substrate and the first semiconductor material layer includes
forming trenches in the second semiconductor substrate and the first semiconductor material layer;
filling the trenches with a dielectric material;
performing a second polishing process to the dielectric material; and
recessing the dielectric material to form the first fin and the second fin.
11. The method of claim 1 , wherein the forming a dielectric material layer on a sidewall of the second semiconductor substrate within the trench includes depositing least one of silicon nitride, silicon oxide, and titanium nitride; and performing an anisotropic etching process.
12. The method of claim 1 , further comprising forming a first field-effect transistor (FET) having a negative conductivity on the first fin in the first region and a second FET having a positive conductivity on the second fin in the second region.
13. A method, comprising:
bonding a first semiconductor substrate and a second semiconductor substrate such that corresponding crystalline directions <001> have a 45-degree angle;
etching the second semiconductor substrate such that a portion of the second semiconductor substrate within a first region remains and a portion of the second semiconductor substrate within a second region is removed to expose the first semiconductor substrate in a trench;
forming a dielectric material layer on a sidewall of the second semiconductor substrate within the trench;
epitaxially growing a first semiconductor layer of a first semiconductor material over the first semiconductor substrate within the second region; and
patterning the second semiconductor substrate in the first region and the first semiconductor layer in the second region to form a first fin in the first region and a second fin in the second region, wherein the first fin is oriented in a first direction and has a crystalline direction <100> along the first direction, wherein the second fin is oriented in the first direction and has a crystalline direction <110> along the first direction.
14. The method of claim 13 , wherein the forming a dielectric material layer on a sidewall of the second semiconductor substrate within the trench includes depositing at least one of silicon nitride, silicon oxide, and titanium nitride; and performing an anisotropic etching process to the dielectric material layer.
15. The method of claim 13 , wherein the bonding a first semiconductor substrate and a second semiconductor substrate includes bonding the first and second semiconductor substrates by a silicon oxide layer sandwiched between the first and second semiconductor substrates.
16. The method of claim 15 , wherein the etching the second semiconductor substrate within the second region includes etching through the silicon oxide layer until the first semiconductor substrate is exposed within the second region, and further recessing the first semiconductor substrate within the second region.
17. The method of claim 13 , further comprising epitaxially growing a second semiconductor layer of a second semiconductor material directly on the first semiconductor substrate within the second region before the epitaxially growing a first semiconductor layer of a first semiconductor material, wherein
the first and second semiconductor substrates are silicon substrates;
the first semiconductor material includes silicon germanium; and
the second semiconductor material includes silicon.
18. A method, comprising:
bonding a first semiconductor substrate and a second semiconductor substrate such that corresponding crystalline directions <001> have a 45-degree angle, wherein the first and second semiconductor substrates are silicon substrate;
forming a patterned mask on the second semiconductor substrate to cover a first region and expose a second region;
etching the second semiconductor substrate within the second region to expose the first semiconductor substrate within a trench;
forming a dielectric material layer on a sidewall of the second semiconductor substrate within the trench;
epitaxially growing a silicon germanium layer over the first semiconductor substrate within the second region and on a sidewall of the dielectric material layer; and
patterning the second semiconductor substrate and the silicon germanium layer to form a silicon fin in the first region and a silicon germanium fin in the second region, wherein the silicon fin is oriented in a first direction and has a crystalline direction <100> along the first direction, wherein the silicon germanium fin is oriented in the first direction and has a crystalline direction <110> along the first direction.
19. The method of claim 18 , wherein
the bonding a first semiconductor substrate and a second semiconductor substrate includes bonding the first and second semiconductor substrates by a silicon oxide layer; and
the etching the second semiconductor substrate within the second region includes further etching through the silicon oxide layer until the first semiconductor substrate is exposed within the second region, and further recessing the first semiconductor substrate within the second region.
20. The method of claim 19 , prior to the epitaxially growing a silicon germanium layer, further comprising epitaxially growing a silicon layer directly on the first semiconductor substrate within the second region such that a top surface of the silicon layer is coplanar with a top surface of the silicon oxide layer.