IP Library Granted Patent US 12,317,469
Granted Patent B2
US 12,317,469 · App. 17/773,068 · Granted May 27, 2025

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Hiroki Komagata (Kanagawa, JP); Yoshihiro Komatsu (Kanagawa, JP); Shinya Sasagawa (Kanagawa, JP); Takashi Hamada (Kanagawa, JP); Yasumasa Yamane (Kanagawa, JP); Shota Mizukami (Hokkai-do, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10B12/00H10D30/6734H10D30/6755H10D86/423H10D86/481H10D86/60H10D87/00H10D99/00
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Quick Facts
Patent No.
US 12,317,469
App. No.
17/773,068
Granted
May 27, 2025
Kind
B2
Abstract

To provide a semiconductor device with less variations in characteristics. The semiconductor device includes a first circuit region and a second circuit region over a substrate, where the first circuit region includes a plurality of first transistors and a first insulator over the plurality of first transistors; the second circuit region includes a plurality of second transistors and a second insulator over the plurality of second transistors; the second insulator includes an opening portion; the first transistors and the second transistors each include an oxide semiconductor; a third insulator is positioned over and in contact with the first insulator and the second insulator; the first insulator, the second insulator, and the third insulator inhibit oxygen diffusion; and the density of the plurality of first transistors arranged in the first circuit region is higher than the density of the plurality of second transistors arranged in the second circuit region.

Claims (55)

1. A semiconductor device comprising:

a first circuit region and a second circuit region over a substrate,

wherein the first circuit region comprises:

a plurality of first transistors; and

a first insulator over the plurality of first transistors,

wherein the second circuit region comprises:

a plurality of second transistors; and

a second insulator over the plurality of second transistors,

wherein the second insulator includes an opening portion,

wherein the first transistors and the second transistors each include an oxide semiconductor,

wherein a third insulator is positioned over and in contact with the first insulator and the second insulator, and

wherein density of the plurality of first transistors arranged in the first circuit region is higher than density of the plurality of second transistors arranged in the second circuit region.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor includes at least any one selected from In, Ga, and Zn.

3. The semiconductor device according to claim 1 , wherein the third insulator is in contact with a side surface of the second insulator in the opening portion.

4. The semiconductor device according to claim 1 , wherein the first insulator, the second insulator, and the third insulator inhibit oxygen diffusion.

5. A semiconductor device comprising:

a first circuit region, a second circuit region, and a third circuit region over a substrate,

wherein the first circuit region comprises:

a plurality of first transistors; and

a first insulator over the plurality of first transistors,

wherein the second circuit region comprises:

a plurality of second transistors; and

a second insulator over the plurality of second transistors,

wherein the second insulator includes a first opening portion,

wherein the third circuit region comprises:

a plurality of third transistors; and

a third insulator over the plurality of third transistors,

wherein the third insulator includes a second opening portion,

wherein the first transistors, the second transistors, and the third transistors each include an oxide semiconductor,

wherein a fourth insulator is positioned over and in contact with the first insulator, the second insulator, and the third insulator,

wherein density of the plurality of first transistors arranged in the first circuit region is higher than density of the plurality of second transistors arranged in the second circuit region and density of the plurality of third transistors arranged in the third circuit region,

wherein the density of the plurality of second transistors arranged in the second circuit region is higher than the density of the plurality of third transistors arranged in the third circuit region, and

wherein a proportion of a total area of the first opening portion in the second circuit region is lower than a proportion of a total area of the second opening portion in the third circuit region.

6. The semiconductor device according to claim 5 , wherein the oxide semiconductor includes at least any one selected from In, Ga, and Zn.

7. The semiconductor device according to claim 5 , wherein the fourth insulator is in contact with a side surface of the second insulator in the first opening portion and a side surface of the third insulator in the second opening portion.

8. The semiconductor device according to claim 5 , wherein the first insulator, the second insulator, the third insulator, and the fourth insulator inhibit oxygen diffusion.

9. The semiconductor device according to claim 5 ,

wherein the first insulator, the second insulator, and the third insulator each include aluminum oxide or silicon nitride, and

wherein the fourth insulator includes aluminum oxide or silicon nitride.

10. A semiconductor device comprising:

a first circuit region and a second circuit region over a substrate,

wherein the first circuit region comprises:

a plurality of first transistors; and

a first insulator over the plurality of first transistors,

wherein the second circuit region comprises:

a plurality of second transistors; and

a second insulator over the plurality of second transistors,

wherein the second insulator includes an opening portion,

wherein the first transistors and the second transistors each include an oxide semiconductor,

wherein a third insulator is positioned over and in contact with the first insulator and the second insulator,

wherein the first insulator and the second insulator each include aluminum oxide or silicon nitride,

wherein the third insulator includes aluminum oxide or silicon nitride, and

wherein density of the plurality of first transistors arranged in the first circuit region is higher than density of the plurality of second transistors arranged in the second circuit region.

11. The semiconductor device according to claim 10 , wherein the oxide semiconductor includes at least any one selected from In, Ga, and Zn.

12. The semiconductor device according to claim 10 , wherein the third insulator is in contact with a side surface of the second insulator in the opening portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2022
From: YAMAZAKI, SHUNPEI; KOMAGATA, HIROKI; KOMATSU, YOSHIHIRO; SASAGAWA, SHINYA; HAMADA, TAKASHI; YAMANE, YASUMASA; MIZUKAMI, SHOTA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 059770/0167 →
Priority Claims (2)
JP 2019-203249 · Nov 8, 2019 · national
JP 2019-203250 · Nov 8, 2019 · national
Continuity (1)
Related Publication 20220399338A1 · Dec 15, 2022
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