Programming operation of memory device being switched from high-density mode to high speed mode and/or lower power mode
Memory devices and methods for operating the same are described. The memory devices may include non-volatile memory having a plurality of memory cells, and a controller. The controller may be configured to begin a first programming operation configured to program a first one of the plurality of memory cells with more than one bit of information, terminate the first programming operation in response to detecting a power loss event, and program, with a second programming operation, second and third ones of the plurality of memory cells with the more than one bit of information.
1. A memory device, comprising:
a non-volatile memory comprising a plurality of memory cells; and
a controller configured to:
begin a first programming operation configured to program a plurality of bits of information to a first one of the plurality of memory cells, wherein the first one of the plurality of memory cells has been previously programmed with one or more additional bits of information,
terminate the first programming operation in response to receiving a command from a connected host device to switch from a high-density operation mode to a high speed mode and/or a lower power mode and without reference to a current or impending power loss event, and
program, with a second programming operation, a second one of the plurality of memory cells with the plurality of bits of information.
2. The memory device of claim 1 , wherein:
the first one of the plurality of memory cells is configured as a triple level cell which has already been programmed with the one or more additional bits of information as lower page data prior to the first programming operation, and
the first programming operation is configured to program the plurality of bits of information as upper page data and extra page data to the first one of the plurality of memory cells.
3. The memory device of claim 2 , wherein:
the second programming operation is configured to program the upper page data and the extra page data to the second one of the plurality of memory cells.
4. The memory device of claim 3 , wherein:
the second programming operation is further configured to program the lower page data to a third one of the plurality of memory cells.
5. The memory device of claim 3 , wherein:
each of the first one and the second one of the plurality of memory cells is configured as a multilevel cell (MLC), a triple level cell (TLC), or a quad level cell (QLC).
6. The memory device of claim 1 , wherein:
the second programming operation requires less energy to program the second one of the plurality of memory cells than the first programming operation would have taken to complete.
7. The memory device of claim 1 , wherein:
the second programming operation is configured to program the second one of the plurality of memory cells in less time than the first programming operation would have taken to complete.
8. The memory device of claim 1 , wherein:
the first programming operation is configured to program the first one of the plurality of memory cells with a first plurality of programming pulses, and
the second programming operation is configured to program the second one of the plurality of memory cells with fewer programming pulses than the first plurality of programming pulses.
9. A memory device, comprising:
a non-volatile memory comprising a plurality of memory cells; and
a controller configured to:
begin a first programming operation configured to program a plurality of bits of information to a first one of the plurality of memory cells, wherein the first one of the plurality of memory cells has been previously programmed with one or more additional bits of information,
terminate the first programming operation in response to receiving a command from a connected host device to switch from a high-density operation mode to a high speed mode and/or a lower power mode and without reference to a current or impending power loss event, and
program, with a second programming operation, each of a subset of the plurality of memory cells with one of the plurality of bits of information.
10. The memory device of claim 9 , wherein:
the first one of the plurality of memory cells is configured as a triple level cell which has already been programmed with the one or more additional bits of information as lower page data prior to the first programming operation, and
the first programming operation is configured to program the plurality of bits of information as upper page data and extra page data to the first one of the plurality of memory cells.
11. The memory device of claim 10 , wherein:
the second programming operation is configured to program the upper page data and the extra page data to the separate ones of the subset of the plurality of memory cells.
12. The memory device of claim 11 , wherein:
the second programming operation is further configured to program the lower page data to one of the subset of the plurality of memory cells.
13. The memory device of claim 11 , wherein:
each of the subset of the plurality of memory cells is configured as a single level cell (SLC).
14. The memory device of claim 9 , wherein:
the second programming operation requires less energy to program the subset of the plurality of memory cells than the first programming operation would have taken to complete.
15. The memory device of claim 9 , wherein:
the second programming operation is configured to program the subset of the plurality of memory cells in less time than the first programming operation would have taken to complete.
16. The memory device of claim 9 , wherein:
the first programming operation is configured to program the first one of the plurality of memory cells with a first plurality of programming pulses, and
the second programming operation is configured to program each of the subset of the plurality of memory cells with fewer programming pulses than the first plurality of programming pulses.
17. A method of operating a memory device having a plurality of memory cells, the method comprising:
initiating a first programming operation configured to program a plurality of bits of information to a first one of the plurality of memory cells, wherein the first one of the plurality of memory cells has been previously programmed with one or more additional bits of information,
terminating the first programming operation in response to receiving a command from a connected host device to switch from a high-density operation mode to a high speed mode and/or a lower power mode and without reference to a current or impending power loss event, and
programming, with a second programming operation, a second one of the plurality of memory cells with the plurality of bits of information.
18. The method of claim 17 , further comprising:
programming, with the second programming operation, a third one of the plurality of memory cells with the one or more additional bits of information.